I am new to embedded programming... From the C6678 examples I load or program each of the 8 core independently. Do I have to write individual programs for each of the 8 cores or can I write one program that can scale automatically? I have seen the image processing example that has a master and slave programs. Is this the way to do it or are there some SYS/BIOS libraries/tools that would allow me to automatically scale from a single multi-threaded program... Any information would be appreciated.
-Chad Sixt
Hi,
There are below options:
1. You can certainly make single out file which can be loaded in all the cores and in those out files, as per the CPU core number you can have different cores doing different tasks.
OR
2. You can also have separate out file and separate project for each of the cores and each of the cores doing its own operation.
3. You can use OpenMP programming in your source code and load the same out file in all the cores and optimize your code for all cores.
Each of the above approach has its own advantage and disadvantage. e.g. approach#2 is the most efficient code size wise and approach#1 and 3 are easy to code and maintain. As a quick start, i would suggest you building the hello world example code for each of the cores and read the core number and print it from each core. Then you can load and run the out file in each of the cores.
Please let us know if you have any queries or questions.
Regards,
Bhavin
OK. Thanks, It appears that it is flexible and hat I have a lot of options. I have been able to get the Hello world program you suggested working and what I would really like to do is as follows:
1. Create some sample data on core1 signal data ( I have an example I can use for this)
2. Send that data (or trigger) to a method on Core2, process or change the data somehow (simulate Algorithm #1)...
3. Send the modified data to (or trigger) a method on Core3, process or change the data somehow (simulate algorithm #2)...
4. Repeat for all the cores 4,5,6,and 7...
5. Send the data to core 8 format and ship the data out the Ethernet to a PC (where is can be saved to a file) I have a PC application that will handle the socket connection and the writing to file…
What is the best approach to achieve this, write individual programs for each core to execute their respective algorithm? Do I need to use IPC for the inter processor calls? This seems ridged. Or do I just want to write the code to as a single program, and let something like OpenMP, optimize the execution. Being an higher level applications developer the "where to run" considerations are relatively new for me...
Thanks again,
Chad
PS: I have the TMDSEVM6678 Evaluation Module that is working great, for running the examples and making small changes anyway...
Texas Instrument SPRAB27A Multicore Programming Guide can help. TI also supply the MAD tool (in the MCSDK) to build multi-core application
Hi Jonathan,I'm trying to do the same thing,I think that you must use IPC for the inter processor calls, the IPC example works fine using MessageQ, but I couldn't figure out a way to send data along with the message, can anyone help me? About OpenMP I think it's not supported yet. I'm using CCS 5.1 and C6000 Compiler 7.3.1 and it doesn't recognize the <omp.h> and the OpenMP directives, maybe there's a linking or compiling option that I'm not using? Regards
I have MessageQ example which runs fine, i will send you the example soon. About OpenMP, have you tried running the OpenMP standard example which comes with release?
Hi Jonathan and 'joh 123456',
The example implementation approach highlighted below should hopefully help answer your questions.
1. Define "DDR3" (or wherever you want system heap) in your RTSC platform file or Linker command file (you can find a sample linker command file at http://processors.wiki.ti.com/index.php/Linker_CMD_Files_for_CCS#C6000)
2. In your Configuration (.cfg) file, you would have (among other things) something like:
var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ')var SYSTEM_HEAPSIZE = 0x00400000; //vary based on your requirement
var NUM_CORES = 2; //vary based on your requirement
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');var heapMemParams = new HeapMem.Params();heapMemParams.size = SYSTEM_HEAPSIZE;heapMemParams.sectionName = "systemHeap";Program.global.heap0 = HeapMem.create(heapMemParams);Program.global.HEAPID = NUMCORES; Program.sectMap["systemHeap"] = "DDR3";var HeapMultiBuf = xdc.useModule('ti.sysbios.heaps.HeapMultiBuf');var heapMultiBufParams = new HeapMultiBuf.Params(); heapMultiBufParams.numBufs = <number of buffers you need>;heapMultiBufParams.blockBorrow = false;heapMultiBufParams.bufParams = [ {blockSize: <size of block you need>, numBlocks:<number of blocks you need>, align:<alignment>, sectionName:"systemHeap"}, ....];Program.global.HEAPMULTIBUF = HeapMultiBuf.create(heapMultiBufParams);
3. In the code for sender core you would add something like:
#include <ti/sysbios/heaps/HeapMultiBuf.h>#define CACHE_LINE_SIZE 128#define bufferSize 20typedef struct Buffer_Msg_s { MessageQ_MsgHeader hdr; Ptr ptr; // pointer to your data uint_least32_t len; } Buffer_Msg;
Ptr pBuffer;
pBuffer = (Ptr)HeapMultiBuf_alloc(HEAPMULTIBUF, bufferSize, CACHE_LINE_SIZE, NULL);
Buffer_Msg *msgBuffer;
msgBuffer = (Buffer_Msg *)MessageQ_alloc(HEAPID, sizeof(Buffer_Msg));
MessageQ_put( <queue id>, (MessageQ_Msg)msgBuffer );HeapMultiBuf_free(HEAPMULTIBUF, pBuffer, bufferSize);
You would have a corresponding MessageQ_get to receive the pointer.
Please note that the above code snippet is just that and is not the complete solution. Please go through http://www.ti.com/lit/ug/sprugo6c/sprugo6c.pdf for more details on IPC, MessageQ, HeapMP and other related information to configure the setup for your use-case. There are also some demos that may be of interest to you here: MCSDK's Image Processing Demo (http://processors.wiki.ti.com/index.php/MCSDK_Image_Processing_Demonstration_Guide) and MIDAS (OCTv1.0 http://processors.wiki.ti.com/index.php/MIDAS_OCT_v1.0_Demo and MIDAS Ultrasound v4.0 http://processors.wiki.ti.com/index.php/MIDAS_Ultrasound_v4.0_Demo). These demos show case approaches to leverage IPC, BIOS and other TI software components to process input data on multiple cores and manage message passing and inter-core communication, and finally output the data via ethernet.
Wrt OpenMP, you can expect to see an MCSDK version later this month that provides OpenMP support. Wrt compiler versions, 7.4.x onwards are set to support the package.
- Uday
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Can you provide some commends to the code? just would like to know what is actually being done where..
-Thanks,
Commends... funny... I meant Comments...
Thanks for your answers.
Bhavin, is your example the same of Gurnani?
Gurnani, thanks for the code, I'm gonna try it too.
There's a new version of IPC userguide (SPRUGO6D) that can be found at: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/1_24_00_16/exports/ipc_1_24_00_16/docs/IPC_Users_Guide.pdf
Thanks again.
Regards
Yes, my example is same as Uday Gurnani.