Hi,
I got this error while running a project on EVMC6687LE. CCS 5.1.1, on Linux.
I'm running a big library, which requires big heap memory. I've place heap memory to DDR3 and increasead its size, then I got this error while booting:
(With smaller heap, the system boots and run, until I call the library and the heap memory is completely filled and the system crashes)
[C66xx_0] [C66xx_0] [C66xx_0] MCSDK IMAGE PROCESSING DEMONSTRATION[C66xx_0] [C66xx_0] QMSS successfully initialized [C66xx_0] CPPI successfully initialized [C66xx_0] PA successfully initialized [C66xx_0] EVM in StaticIP mode at 192.168.0.225[C66xx_0] Set IP address of PC to 192.168.0.98[C66xx_0] Starting webfiles_add[C66xx_0] Done webfiles_add[C66xx_0] HTTP Status Added[C66xx_0] Debug Message Level Added[C66xx_0] Last while[C66xx_0] PASS successfully initialized [C66xx_0] Ethernet subsystem successfully initialized [C66xx_0] Ethernet eventId : 48 and vectId (Interrupt) : 7 [C66xx_0] Registration of the EMAC Successful, waiting for link up ..[C66xx_0] Network Added: If-1:192.168.0.225 [C66xx_0] Service Status: HTTP : Enabled : : 000[C66xx_0] A0=0x0 A1=0x0[C66xx_0] A2=0x0 A3=0x80002448[C66xx_0] A4=0x90 A5=0x15000103[C66xx_0] A6=0xd0 A7=0x0[C66xx_0] A8=0x1844018 A9=0x1[C66xx_0] A10=0x90 A11=0x8000[C66xx_0] A12=0x1d0c0300 A13=0x80002448[C66xx_0] A14=0x0 A15=0x0[C66xx_0] A16=0xc207c80 A17=0xc[C66xx_0] A18=0x80000d54 A19=0x0[C66xx_0] A20=0x0 A21=0x0[C66xx_0] A22=0x0 A23=0x0[C66xx_0] A24=0x0 A25=0x0[C66xx_0] A26=0x0 A27=0x0[C66xx_0] A28=0x0 A29=0xe100a8c0[C66xx_0] A30=0x0 A31=0x1[C66xx_0] B0=0x36f6 B1=0x0[C66xx_0] B2=0x0 B3=0x8820de50[C66xx_0] B4=0x0 B5=0xc08aed4[C66xx_0] B6=0xe600010 B7=0x883d3138[C66xx_0] B8=0x883d51a8 B9=0x15000102[C66xx_0] B10=0xc087e4c B11=0x90[C66xx_0] B12=0x0 B13=0x0[C66xx_0] B14=0x809b88 B15=0x809a90[C66xx_0] B16=0x0 B17=0xc08a138[C66xx_0] B18=0xc07f8f7 B19=0x10[C66xx_0] B20=0x80000548 B21=0x4[C66xx_0] B22=0xd B23=0x0[C66xx_0] B24=0x3000 B25=0x0[C66xx_0] B26=0x2e2 B27=0x0[C66xx_0] B28=0x0 B29=0xc0[C66xx_0] B30=0x0 B31=0x0[C66xx_0] NTSR=0x1020f[C66xx_0] ITSR=0xd[C66xx_0] IRP=0x88251f80[C66xx_0] SSR=0x0[C66xx_0] AMR=0x0[C66xx_0] RILC=0x0[C66xx_0] ILC=0x0[C66xx_0] Exception at 0x8000246c[C66xx_0] EFR=0x2 NRP=0x8000246c[C66xx_0] Internal exception: IERR=0x8[C66xx_0] Opcode exception[C66xx_0] ti.sysbios.family.c64p.Exception: line 248: E_exceptionMin: pc = 0x88251f80, sp = 0x00809a90.[C66xx_0] To see more exception detail, use ROV or set 'ti.sysbios.family.c64p.Exception.enablePrint = true;'[C66xx_0] xdc.runtime.Error.raise: terminating execution
The exception is for an illegal OpCode. I'd open a disassembly window at the NRP and see what was there. Does it look like code or data.
Any number of issues could have cause this, ran off into the weeds because of bad pointer, data corruption, overwrote program space with data due to buffer overflow, etc. The only way to determine why it happened is to start debugging. Look at where the CorePac was executing when the Exception occurred (i.e. NRP)
You may also want to consider using CP_Tracer to trace the program.
Best Regards,
Chad
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I have exactly the same problem. Every thing works fine with small heap, but with bigger heap, my program crash with the same exception.
In your case, what is the solution ?
Thanking you in advance,
Jean-Baptiste
I've got a weird error with big heap/stack and the Idle Thread.
Every time I place heap/stack into DDR3 in order to fit my size requirements, some weird problem related to sysbios.knl.task module happens.
So far, I've noticed that disabling the IdleTask at .cfg files seems to solve the problem. But I'm not so sure about that.
Please check my other posts, on a few of them there are more valuable responses from TI staff.
Weber
Hi weber,
Thank for your answer. I use disassembly view right now ... I will try without Idle task.
Thanks,
Could you share here a snap from the disassembly around NPR's location?
I'n my case, the processor jumped into code data, while disassembly the code for similar problem.
I'm still in trouble without Idle task, but no more exception ... Just crash !
I rebuild to have exception and I share here the disassembl around NPR.
Ok. The disassembly piece of code around NPR should give at least a clue of what happened.
Have you disable using?:
Task.enableIdleTask = false;Task.allBlockedFunc = Idle.run;
Yes, I use your code on .cfg.
Please find my snap :
makeCrsp:8357f4e0: 441AB29E [ B1] LDBU.D2T2 *+B15[6834],B88357f4e4: 44898000 [ B1] NOP 138357f4e8: 44A28000 .word 0x44a280008357f4ec: 00000002 NOP 8357f4f0: 06FC0000 NOP 8357f4f4: 00000001 NOP 8357f4f8: 00010000 || NOP 98357f4fc: 00000032 MPY2.M2 B0,B0,B1:B08357f500: 00000003 NOP 8357f504: 42800000 || [ B1] NOP 8357f508: 3F800000 [!B0] NOP 8357f50c: FFFFFFFB .word 0xfffffffb8357f510: 00010001 || NOP 98357f514: 0000 || ADD.L1 A0,A0,A08357f516: 0000 ADD.L1 A0,A0,A08357f518: 03201861 DADD.S1X 0,B9:B8,A7:A68357f51c: E4000001 .fphead n, l, W, BU, nobr, nosat, 0100000b8357f520: CCCD LDW.D2T1 *B15[6],A48357f522: 3E4C LDBU.D1T2 *A4++[2],B48357f524: 3E4CCCCD || [!B0] LDH.D2T1 *+B15[19660],A288357f528: 100F1413 || CALLP.S2 __strasgi_64plus (PC+30880 = 0x83586dc0),B38357f52c: 3851B717 || .word 0x3851b7178357f530: 0000 || ADD.L1 A0,A0,A08357f532: 8F32 || MVK.S1 172,A68357f534: 023C9058 || ADD.L1X 4,B15,A4
makeCrsp is one of my function, and if I use L2SRAM rather than DDR3, it works fine. The exception looks appear during NOP ... That is weird !
Thanking you in advance if you have any idea
Once NOP stands for No Operation Performed, I also have no specific idea about the error.
However, one thing crossed my mind: To where the processor goes after a NOP instruction? I'm not much a assembly guy, but IF it goes to the next instruction it will rise a crash, because the next instruction is data definition (.word). Maybe the TI's assembly language tools users guide answers it.
The assembly user guide for C66 is SPRU186V.8484.SPRU186V.pdf
If you open a new thread to this problem, please let me know, I want to follow the discussions.
I remove my last question ;) It is obvious.
I see that one TI employe talk about L2 Cache. I am going to make some try without L2 cache
Just check my other post: http://e2e.ti.com/support/embedded/bios/f/355/p/187339/674520.aspx#674520
There it is well-enough explained a TI's guy.
I've checked it. The processor goes to the next instruction.
Once .word isn't a valid processor instruction, the system crashes just as mine that I've reported on the other post.
Jean-Baptiste,
The "Code" looks like garabage, I'd guess something overwrote this (possibly buffer overflowing.) Can you go back and load the code and dump the dissassembly at the same location after loading the code. If you compare the two I'd bet you have something drastically different. Also, look at your buffers that are mapped immediately before this section of code. That's what you'd most likely have overflowing.
The debugger shouldn't report the overflow prior to the final error?
Weber,
These are not HW buffers (Heaps, Stack, etc) These buffers are using memory in the same space as everything else that's out there in DDR in this case. There's nothing to prevent you from overflowing the buffer, you need to make it sufficiently large. I'd guess the reason you didn't see it when you moved code to another space, is you left the buffer out in DDR, hence the overflow didn't affect anyone.
Note, this is why I suggested to take a look at the dissassembly. So you could see if it was garbage or not, as this was one of the reasons you would have had the failure, that is executing invalid opcodes which is what the error message was. Either it jumped to an area with garbage code, or something overwrote the code w/ garbage.
Best Regards,Chad