Hi,
I am looking for documentation on the behavior of core0 when it is 'local reset' by another c6678 core, or in my case by a remote master via PCIe. I can see (via jtag experiments) that cores 1-7 jump to the boot rom, eventually landing at 0x20b002a8 where they sit in IDLE until an IPC interrupt causes them to wakeup and check the MAGIC address. Core0 does something else though. It jumps to boot rom, eventually looping around address 0x20b0c952, but not executing an IDLE instruction. Can someone tell me what it is doing here? If I send it an IPC interrupt, will it poll the MAGIC address like the other cores do?
Thanks,
Joel
Are you sure you are doing local reset seems like it is a system reset. Also i beleive you have 3 seperate threads. Can we just follow up on one and if you can summarize in one thread that will be great.
Arun.
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Also please let me know what prcess you are usin to trigger the reset through PCIe.
thanks,
arun.
Sorry about the multiple threads. I'll stick to this one from now on. As mentioned on the other thread, I believe that I am doing a local reset, however, since I have not set DSP_BOOT_ADDRx register, the register still contains the boot-rom entry address.
To trigger the reset through PCIe, I do the following (pseudo-code):
#define PSC_REGISTERS 0x02350000 #define MDCTL_CORE0_OFFSET 0xA3C #define MDCTL_LRST_BITMASK 0x00000100
reset_core(int core_num) {
reg_addr = PSC_REGISTERS + MDCTL_CORE0_OFFSET + (0x4 * core_num);
reg = readRegister(reg_addr);
writeRegister(reg_addr, reg & ~MDCTL_LRST_BITMASK);
msleep(1);
writeRegister(reg_addr, reg | MDCTL_LRST_BITMASK);
}
so basically asserting the local reset bit in the core's MDCTL register, waiting a millisecond, then de-asserting the local reset bit. Is there anything else I should be doing?
Hi Arun,
So now that I know about the role of the DSP_BOOT_ADDRx registers, I have another question:
What is the relationship between the DSP_BOOT_ADDRx register and the BOOT MAGIC address (0x87fffc)? What I mean is, if you take a look at the pcie bootloader 'hello world' example ( at mcsdk_2_00_07_19/tools/boot_loader/examples/pcie/pcieboot_helloworld/src/pcieboot_helloworld.c ),
I believe that it starts cores 1-7 executing by writing to the BOOT MAGIC address, and then triggering an inter-core interrupt via writing to IPCGR(x). Receiving this interrupt somehow causes the core which was executing an IDLE instruction to examine the BOOT MAGIC address and then start executing from that entry point. It seems like the code could almost equivalently set DSP_BOOT_ADDRx, and then issued a local reset.
Could you explain why there are these two mechanisms, and when you would use one vs the other?
Boot magic address is used by rom boot code(RBL), while the DSP_BOOT_ADDR is used by the core. So when ever the RBL comes into the picture, it uses the boot magice address. BTW for RBL, the boot magic address is used even for core0.
Excellent. Thanks Arun!