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Digital Signal Processors (DSP)
C6000 Multicore DSP
Keystone Multicore Forum (C66, 66A, AM5)
About the interrupt of TMS320C6678
As the datasheet of 6678 said
The interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP) , or the advanced emulation logic.
but why are there so many events input to INTC,more than 128? thanks a lot.
First the picture you have appears to be from an pre-release version of the Data Manual. You may want to check and get the latest version from the TMS320C6678 Product Page.
The 128-system events programmed to the CorePac are the amount that can be feed to each CorePac - There is a CIC at each CorePac not just the 4 System Level CIC's (in your capture they are labeled INTC0-INTC3, but this is old, and they should be labeled CIC0-CIC3.) The CIC0-CIC3 reduces the total events that are in the Core-only Secondary, Common and Reserved Events down to a limited subset (17 Secondary and 8 Broadcast that go to all cores) and this combined with the 98 Primary Events (yours shows 71, but it's 98 in the release version) which is within the 128-events to be mapped to the CorePac's CIC.
Please click the Verify Answer button on this post if it answers your question.
Thanks a lot.
Do you mean there are two CIC .one is System Level CIC and the other is CorePac's CIC.
System Level CIC(in my capture they are labeled INTC0-INTC3)reduce the total events(more than 128) down to 128 events.CorePac's CIC allows for up to 128 events to be programmed to any of the twelve CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP) , or the advanced emulation logic?
Does MCSDK provide the example about interrupt of 6678evm?which one?
Yes, that's a correct understanding. There's examples in the PDK pdk_C6678_1_0_0_17\packages\ti\csl\example\cpintc
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