Hi All,
I'm trying to study the FFT coprocessor functionality as it needed to be included in to my main project. So, a FFTC standalone project has been created and according to my main project requirements the "systemHeap",& " .far" sections are reallocated from L2SRAM to DDR3 in user defined link.cmd file. After this modification the program is not executing and hanging up just before following functiion call "memset (pReqBuffer, 0, maxReqBufferLen)".
As my main project consuming more that 4MB of heap memory, I've done above changes. Are there any restriction on system heap utilization, or Am'I missing any thing in initializations of DDR3..? Please help me in resolve the issue.
I'm using TMS320C6670 EVM.
Thanks in advance
Madhu K
Madhu,
If your program is hanging up just before calling memset(), how can we guess what might be wrong since we know nothing about what code is executing before memset()? Instead of telling us what is after the point of failure, can you please mention what is happening at the point of failure?
It is very difficult for me (maybe only me) to read the highlighted portions of your posting. Please find a better way to highlight, or underline, or Bold font, or no highlighting; it will help old eyes such as mine.
Look in your linker .map file to find out where the two DDR3 sections are actually allocated by the linker.
Run the program up to the point of the failure, stopping just before the failure, and look at the DDR3 .far and other section in a Memory Browser window. If you are able to read and write to locations there, then everything is good with the initialization. If not, then something needs to be fixed in the initialization. This is done in a GEL file when using the emulator, but must be done in your bootloader code when running the real application from reset and bootloading.
Regards,RandyP
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Hi RandyP,
Thanks for your prompt reply and I regret the inconvenience. With your suggestions I have checked my code, and following are my observations....
1) Whenever .far and .system sections are placed in DDR3, some garbage value is assigning to the variable "maxReqBufferLen" within the function call 'memset (pReqBuffer, 0, maxReqBufferLen)". The memset function is placed at lline number #280, in the file " FFTC_singlecore.c".
2) The same "maxReqBufferLen" variable getting correct value, when .far and .system sections are placed in L2SRAM or MSMCSRAM using .cmd file.
3) I'm attaching the test project for your reference.
5127.FFTC_TI_21MAY12.rar
Regards
Someone else may jump in around me and debug your code for you, but I am not in a position to do that. And reading someone's code is not an efficient way to figure out what is wrong with it. I will try to guide you to finding your problem, with your help.
Look in your linker .map file to find out where the two DDR3 sections are actually allocated by the linker. Where are they allocated? What is the address of the maxReqBufferLen variable?
Run the program up to the point of the failure, stopping just before the failure, and look at the DDR3 .far and .system sections in a Memory Browser window. Are you able to read and write to locations there?
When you say
Madhusome garbage value is assigning to the variable "maxReqBufferLen" within the function call 'memset (pReqBuffer, 0, maxReqBufferLen)"
do you mean that the third argument is changed inside the execution of the memset library function or that the variable maxReqBufferLen has a corrupted value before memset is called? In other words, if you set a breakpoint at the memset function call and run to that breakpoint, does the variable maxReqBufferLen have a corrupted value already?
Thanks for the reply. In fact, this problem persisting when I change .far, .sysmem and systemHeap parameters to DDR3, as I mentioned in the opening conversation. So, my question is how to configure DDR3 for system Heap, I mean, is there any particular procedure for initializing DDR3 in SYS/BIOS. The following lines are depict the project link.cmd (user defined), in which two changes are causing problem. If I revert to L2SRAM the test project working perfectly.
SECTIONS{ .text: load >> DDR3 .ti.decompress: load > L2SRAM .stack: load > L2SRAM GROUP: load > L2SRAM { .bss: .neardata: .rodata: } .cinit: load > MSMCSRAM .pinit: load >> L2SRAM .init_array: load > L2SRAM .const: load >> MSMCSRAM .data: load >> L2SRAM .fardata: load >> MSMCSRAM .switch: load >> L2SRAM .sysmem: load > DDR3 // L2SRAM .far: load >> DDR3 //L2SRAM .args: load > L2SRAM align = 0x4, fill = 0 {_argsize = 0x0; } .cio: load >> L2SRAM .ti.handler_table: load > L2SRAM systemHeap: load >> L2SRAM .vecs: load >> L2SRAM xdc.meta: load >> MSMCSRAM, type = COPY}
Thanks & Regards
Please answer the questions I have asked above. There is nothing obvious that is wrong in your linker command file edits.
Try putting the two sections into MSMCSRAM to see if it works there.
I think a good point to remember here is that the L2SRAM is individual for each core through a mirroring system. Therefore is the systemHeap is in L2SRAM, then each core can happily work through its own stack and heap without crushing another cores. As soon as you move it to DD3, each core is now using the exact same memory address for the system memory as every other core and they are potentially allocating the same locations over and over again. This is becuase the cores do not know what the other cores have allocated. You will get one hot mess in this case. the same is true if you move it to MSMCSRAM becuase each core addresses it the same as DDR3
I am sorry Randy has not pointed this out clearly to you. He seems quite unwilling to really understand your problem. He wouldn't have even had to look at code to figure this out.
What you need to do (if you want to put the systemmem in DDR3) is create a memory section and individual heaps for each core to work with you allocate memory or create a task.
Here is some of my config file showing this, I am not sure how you would do this exactly in the user defined linker file. I was working the RTSC application. Now what I did was create a .myHeapSection and create 7 heaps (one each of my active cores) in this section. (I actually do this several times for different parts of my application but that is beside the point.) Then, I place this section in DDR3.
heapMemParams.size = 2000*1024;//Task.defaultStackSize;
heapMemParams.sectionName = ".myHeapSection";
Program.global.myHeap0 = HeapMem.create(heapMemParams);
Program.global.myHeap1 = HeapMem.create(heapMemParams);
Program.global.myHeap2 = HeapMem.create(heapMemParams);
Program.global.myHeap3 = HeapMem.create(heapMemParams);
Program.global.myHeap4 = HeapMem.create(heapMemParams);
Program.global.myHeap5 = HeapMem.create(heapMemParams);
Program.global.myHeap6 = HeapMem.create(heapMemParams);
Program.global.myHeap7 = HeapMem.create(heapMemParams);
heapMemParams.size = 0x320000; //Size of 1280*1280
heapMemParams.sectionName = ".myScratchSection";
Program.global.myScratch1 = HeapMem.create(heapMemParams);
Program.global.myScratch2 = HeapMem.create(heapMemParams);
Program.global.myScratch3 = HeapMem.create(heapMemParams);
Program.global.myScratch4 = HeapMem.create(heapMemParams);
Program.global.myScratch5 = HeapMem.create(heapMemParams);
Program.global.myScratch6 = HeapMem.create(heapMemParams);
Program.global.myScratch7 = HeapMem.create(heapMemParams);
heapMemParams.size = 2048*4*4+1024; //numBuffers*MaxBlobSets*4Bytes*4variables + for misc
heapMemParams.sectionName = ".msmcsramHeap";
Program.global.msmcsramHeap1 = HeapMem.create(heapMemParams);
Program.global.msmcsramHeap2 = HeapMem.create(heapMemParams);
Program.global.msmcsramHeap3 = HeapMem.create(heapMemParams);
Program.global.msmcsramHeap4 = HeapMem.create(heapMemParams);
Program.global.msmcsramHeap5 = HeapMem.create(heapMemParams);
Program.global.msmcsramHeap6 = HeapMem.create(heapMemParams);
Program.global.msmcsramHeap7 = HeapMem.create(heapMemParams);
heapMemParams.size = 0x300000;// 4*1024;//0x100;
Program.global.myNetworkHeap0 = HeapMem.create(heapMemParams);
Program.sectMap["systemHeap"] = "L2SRAM";
Program.sectMap[".cio"] = "L2SRAM";
Program.sectMap[".far"] = "L2SRAM";
Program.sectMap[".rodata"] = "L2SRAM";
Program.sectMap[".neardata"] = "L2SRAM";
Program.sectMap[".bss"] = "L2SRAM";
Program.sectMap[".stack"] = "L2SRAM";
Program.sectMap[".nimu_eth_ll2"] = "L2SRAM";
Program.sectMap[".myLocalMemory"] = "L2SRAM";
Program.sectMap[".cinit"] = "L2SRAM"; //might work in DDR3
Program.sectMap[".fardata"] = "L2SRAM";
Program.sectMap[".vecs"] = "L2SRAM";
Program.sectMap[".msmcsramHeap"] = "MSMCSRAM";
Program.sectMap[".srioSharedMem"] = "MSMCSRAM";
Program.sectMap[".imgHeaders"] = "MSMCSRAM_IMG_HDR";
Program.sectMap[".cppi"] = "DDR3";
Program.sectMap[".qmss"] = "DDR3";
Program.sectMap[".const"] = "DDR3";
Program.sectMap[".text"] = "DDR3";
Program.sectMap[".switch"] = "DDR3";
Program.sectMap["platform_lib"] = "DDR3"; //confirm this is only code
Program.sectMap[".myHeapSection"] = "DDR3";
Program.sectMap[".far:taskStackSection"] = "DDR3";
Program.sectMap[".myScratchSection"] = "DDR3_SCRATCH";
Program.sectMap[".resmgr_memregion"] = {loadSegment: "L2SRAM", loadAlign:128}; /* QMSS descriptors region */
Program.sectMap[".resmgr_handles"] = {loadSegment: "L2SRAM", loadAlign:16}; /* CPPI/QMSS/PA Handles */
Program.sectMap[".resmgr_pa"] = {loadSegment: "L2SRAM", loadAlign:8}; /* PA Memory */
Program.sectMap[".far:NDK_OBJMEM"] = {loadSegment: "MSMCSRAM_NDK", loadAlign: 8};
Program.sectMap[".far:NDK_PACKETMEM"] = {loadSegment: "MSMCSRAM_NDK", loadAlign: 128};
Then in the application, when I create the tasks for these cores I allocated their stack specifically from this section. Tasks that don't need that much memory I just let them allocate from the systemmem which you can see is still in L2SRAM. I left alot of the default memory in L2SRAM also, becuase I am not sure how some of the TI libraries are using this so I don't want to cause extra issues. I have control over my application so I moved everything I could control to DDR3 or a blocked of section of MSMCSRAM (for example the MSMCSRAM_NDK section that i created using the platform tool.)
There is the code used to create a task with a systemheap from the config file above:
taskHeaps[0] = myHeap1;
taskHeaps[1] = myHeap2;
taskHeaps[2] = myHeap3;
taskHeaps[3] = myHeap4;
taskHeaps[4] = myHeap5;
Task_Params_init(&taskParams);
taskParams.stackSize =2000*1024;
taskParams.stackHeap = HeapMem_Handle_to_xdc_runtime_IHeap(taskHeaps[CORE_NUM-1]);
if(taskParams.stackHeap == NULL)
{
sprintf(buffer,"No heap initialized.");
ekg_vfib(buffer, CORE_NUM, CORE_NUM);
}
else
Task_create((ti_sysbios_knl_Task_FuncPtr)detectionWorker, &taskParams, NULL);
Hope this helps a bit. I just went through this so if something isn't clear, I can offer more advice if needed.
Brandy
Are you running a multi-core application, or are you currently running a single-core, standalone application to test the use of the FFTC?
Hi Brandy,
Thanks for your valuable suggestions. Now I have changed my configurations file as follows:
/* Create a default system heap using ti.bios.HeapMem. */var heapMemParams1 = new HeapMem.Params;heapMemParams1.size = 8192 * 36;heapMemParams1.sectionName = "systemHeap";Program.global.heap0 = HeapMem.create(heapMemParams1); /Heap creation for "core0"Program.sectMap["systemHeap"] = "DDR3";
But still problem is persisting. Today also I'll try your suggestions and let you know the results.
To RandyP,
Thanks for your follow-up. I'm running single core application and created a stand alone project to study the FFTC application, which will be included later to my main project.
"
2) The same "maxReqBufferLen" variable getting correct value, when .far and .system sections are placed in L2SRAM or MSMCSRAM using .cmd file."
even when the sections are placed in DDr3, i see that the value of the variable maxReqBufferLen is 8192.
I am wondering why you are seeing a different value.
By the way, i am using a simulator to verify this. But i would guess it should work on EVM as well.
Regards,
Kishore.
Hi Kishore,
Glad to see your reply. Now I'm also able to run the program (on simulator) up to this point("fftc.c"/line #2878/ Fftc_osalFree (pRxObjInfo->pOrigAccListAddress, listSize, TRUE)/) and getting the assertion as follows.
[TMS320C66x_0] **************************************************
[TMS320C66x_0] *************** FFTC START ***************[TMS320C66x_0] **************************************************[TMS320C66x_0] [Core 0]: FFTC instance 0 successfully initialized [TMS320C66x_0] Entering setup_PDSCH_FFTC[Core 0]: FFTC driver successfully opened [TMS320C66x_0] Global FDQ 877 successfully setup with 8 descriptors[TMS320C66x_0] Free descriptor queue 878 successfully setup. Descriptors allocated of type (0): 4 [TMS320C66x_0] [Core 0]: FFTC successfully opened [TMS320C66x_0] ti.sysbios.heaps.HeapMem: line 331: assertion failure: A_invalidFree: Invalid free[TMS320C66x_0] xdc.runtime.Error.raise: terminating execution
To see the above console please change .cmd setting as follows:
systemHeap section to "systemHeap: load >> DDR3". even MSMCSRAM also throwing same error.
I'm using C.C.S. Version: 5.1.1.00028
SYS BIOS 6.32.05.54
XDCtools 3.22.04.46
BIOS Multicore SDK 2.00.05.17
And memory configuration in .cfg is as follows:
/* Create a default system heap using ti.bios.HeapMem. */var heapMemParams1 = new HeapMem.Params;heapMemParams1.size = 8192 * 25;heapMemParams1.sectionName = "systemHeap";Program.global.heap0 = HeapMem.create(heapMemParams1);/* This is the default memory heap. */Memory.defaultHeapInstance = Program.global.heap0;Program.sectMap["systemHeap"] = Program.platform.stackMemory;
fftc_linker.cmd configurations:
SECTIONS{ .qmss: load >> DDR3 .cppi: load >> DDR3 .fftc: load >> DDR3 .testData: load >> DDR3 .srioSharedMem: load >> DDR3 .init_array: load >> DDR3}SECTIONS{ .text: load >> DDR3 .ti.decompress: load > L2SRAM .stack: load > L2SRAM GROUP: load > L2SRAM { .bss: .neardata: .rodata: } .cinit: load > MSMCSRAM .pinit: load >> L2SRAM .init_array: load > L2SRAM .const: load >> MSMCSRAM .data: load >> L2SRAM .fardata: load >> MSMCSRAM .switch: load >> L2SRAM .sysmem: load > DDR3 // L2SRAM .far: load >> DDR3 //L2SRAM .args: load > L2SRAM align = 0x4, fill = 0 {_argsize = 0x0; } .cio: load >> L2SRAM .ti.handler_table: load > L2SRAM systemHeap: load >> DDR3 //L2SRAM .vecs: load >> L2SRAM xdc.meta: load >> MSMCSRAM, type = COPY}
If we assign DDR3 to L2SRAM then console will show as follows and this is the expected.
[TMS320C66x_0] [Core 0]: FFTC instance 0 successfully initialized [TMS320C66x_0] Entering setup_PDSCH_FFTC[Core 0]: FFTC driver successfully opened [TMS320C66x_0] Global FDQ 877 successfully setup with 8 descriptors[TMS320C66x_0] Free descriptor queue 878 successfully setup. Descriptors allocated of type (0): 4 [TMS320C66x_0] [Core 0]: FFTC successfully opened [TMS320C66x_0] **************************************************[TMS320C66x_0] ****************** FFTC END **************[TMS320C66x_0] **************************************************
As no progress with my standalone FFTC single core project study, I'm going one step back and studying again TI's "FFTC_Simple_testproject". According to my main project requirements, I pushed code memory and data memory on to DDR3 by creating a new repository. Here are my RTSC configuration settings.
and the console printing as follows.
[C66xx_0] **************************************************[C66xx_0] *************** FFTC Testing Start ***************[C66xx_0] **************************************************[C66xx_0] Using FFTC Driver version: 0x100000e Version Info: FFTC Driver Revision: 01.00.00.14:Jun 5 2012:10:47:06 [C66xx_0] Core 0 : L1D cache size 7. L2 cache size 0.[C66xx_0] [Core 0]: FFTC instance 0 successfully initialized [C66xx_0] [Core 0]: FFTC instance 1 successfully initialized [C66xx_0] Free descriptor queue 878 successfully setup. Descriptors allocated of type (2): 4 [C66xx_0] Free descriptor queue 879 successfully setup. Descriptors allocated of type (0): 4 [C66xx_0] [Core 0]: FFTC successfully opened [C66xx_0] **************************************************[C66xx_0] ************* FFTC LLD Testing Start *************[C66xx_0] **************************************************[C66xx_0] *************** Testing Instance A ***************[C66xx_0] --------------------------------------------[C66xx_0] FFTC LLD Test - MMR Testing START! [C66xx_0] --------------------------------------------[C66xx_0] Fftc_readPidReg() test PASSED [C66xx_0] Fftc_readGlobalConfigReg() test PASSED [C66xx_0] Fftc_writeGlobalConfigReg() test PASSED [C66xx_0] Fftc_doSoftwareReset() test PASSED [C66xx_0] Fftc_doSoftwareContinue() test PASSED [C66xx_0] Fftc_isHalted() test PASSED [C66xx_0] Fftc_readEmulationControlReg() test PASSED [C66xx_0] Fftc_writeEmulationControlReg() test PASSED [C66xx_0] Fftc_readErrorIntRawStatusReg() test PASSED [C66xx_0] Fftc_clearErrorIntRawStatusReg() test PASSED [C66xx_0] Fftc_readErrorIntEnableSetReg() test PASSED [C66xx_0] Fftc_writeErrorIntEnableSetReg() test PASSED [C66xx_0] Fftc_clearErrorIntEnableReg() test FAILED [C66xx_0] Fftc_writeHaltOnErrorReg() test PASSED [C66xx_0] Fftc_readHaltOnErrorReg() test PASSED [C66xx_0] Fftc_readEoiReg() test PASSED [C66xx_0] Fftc_writeEoiReg() test PASSED [C66xx_0] Fftc_readQueueClippingDetectReg() test PASSED [C66xx_0] Fftc_clearQueueClippingDetectReg() test PASSED [C66xx_0] Fftc_readQueueConfigRegs() test PASSED [C66xx_0] Fftc_writeQueueConfigRegs() test PASSED [C66xx_0] Fftc_readDftSizeListGroupReg() test PASSED [C66xx_0] Fftc_writeDftSizeListGroupReg() test PASSED [C66xx_0] fftc_read_blockDestQStatusReg() test PASSED [C66xx_0] fftc_read_blockShiftStatusReg() test PASSED [C66xx_0] fftc_read_blockCyclicPrefixStatusReg() test PASSED [C66xx_0] fftc_read_blockControlStatusReg() test PASSED [C66xx_0] fftc_read_blockFreqShiftStatusReg() test PASSED [C66xx_0] fftc_read_blockPktSizeStatusReg() test PASSED [C66xx_0] fftc_read_blockTagStatusReg() test PASSED [C66xx_0] --------------------------------------------[C66xx_0] FFTC LLD Test - MMR Testing DONE! [C66xx_0] --------------------------------------------[C66xx_0] *************** Testing Instance B ***************[C66xx_0] --------------------------------------------[C66xx_0] FFTC LLD Test - MMR Testing START! [C66xx_0] --------------------------------------------[C66xx_0] Fftc_readPidReg() test PASSED [C66xx_0] Fftc_readGlobalConfigReg() test PASSED [C66xx_0] Fftc_writeGlobalConfigReg() test PASSED [C66xx_0] Fftc_doSoftwareReset() test PASSED [C66xx_0] Fftc_doSoftwareContinue() test PASSED [C66xx_0] Fftc_isHalted() test PASSED [C66xx_0] Fftc_readEmulationControlReg() test PASSED [C66xx_0] Fftc_writeEmulationControlReg() test PASSED [C66xx_0] Fftc_readErrorIntRawStatusReg() test PASSED [C66xx_0] Fftc_clearErrorIntRawStatusReg() test PASSED [C66xx_0] Fftc_readErrorIntEnableSetReg() test PASSED [C66xx_0] Fftc_writeErrorIntEnableSetReg() test PASSED [C66xx_0] Fftc_clearErrorIntEnableReg() test FAILED [C66xx_0] Fftc_writeHaltOnErrorReg() test PASSED [C66xx_0] Fftc_readHaltOnErrorReg() test PASSED [C66xx_0] Fftc_readEoiReg() test PASSED [C66xx_0] Fftc_writeEoiReg() test PASSED [C66xx_0] Fftc_readQueueClippingDetectReg() test PASSED [C66xx_0] Fftc_clearQueueClippingDetectReg() test PASSED [C66xx_0] Fftc_readQueueConfigRegs() test PASSED [C66xx_0] Fftc_writeQueueConfigRegs() test PASSED [C66xx_0] Fftc_readDftSizeListGroupReg() test PASSED [C66xx_0] Fftc_writeDftSizeListGroupReg() test PASSED [C66xx_0] fftc_read_blockDestQStatusReg() test PASSED [C66xx_0] fftc_read_blockShiftStatusReg() test PASSED [C66xx_0] fftc_read_blockCyclicPrefixStatusReg() test PASSED [C66xx_0] fftc_read_blockControlStatusReg() test PASSED [C66xx_0] fftc_read_blockFreqShiftStatusReg() test PASSED [C66xx_0] fftc_read_blockPktSizeStatusReg() test PASSED [C66xx_0] fftc_read_blockTagStatusReg() test PASSED [C66xx_0] --------------------------------------------[C66xx_0] FFTC LLD Test - MMR Testing DONE! [C66xx_0] --------------------------------------------[C66xx_0] --------------------------------------------[C66xx_0] FFTC LLD Test - Helper APIs Testing START! [C66xx_0] --------------------------------------------[C66xx_0] Fftc_compileQueueLocalConfigParams() test PASSED [C66xx_0] fftc_recompile_queueLocalDFTParams() test PASSED [C66xx_0] Fftc_recompileQueueLocalCyclicPrefixParams() PASSED [C66xx_0] Fftc_createDftSizeList() test PASSED [C66xx_0] Fftc_createControlHeader() test PASSED [C66xx_0] Fftc_modifyLocalCfgPresentControlHeader() PASSED [C66xx_0] --------------------------------------------[C66xx_0] FFTC LLD Test - Helper APIs Testing DONE! [C66xx_0] --------------------------------------------[C66xx_0] **************************************************[C66xx_0] ************** FFTC LLD Testing End **************[C66xx_0] **************************************************[C66xx_0] --------------------------------------------[C66xx_0] FFTC-CPPI SINGLECORE MONOLITHIC Test START on Core 0 [C66xx_0] Sample Size: 16 [C66xx_0] Number of Blocks: 5 [C66xx_0] Tx Queue: 0 [C66xx_0] Descriptor Type: Monolithic [C66xx_0] --------------------------------------------[C66xx_0] [Core 0]: Rx Flow 0 opened successfully using Rx queue 708 [C66xx_0] **************************************************[C66xx_0] *************** FFTC Testing Start ***************[C66xx_0] **************************************************[C66xx_0] Using FFTC Driver version: 0x100000e Version Info: FFTC Driver Revision: 01.00.00.14:Jun 5 2012:10:47:06 [C66xx_0] Core 0 : L1D cache size 7. L2 cache size 0.[C66xx_0] [Core 0]: FFTC instance 0 successfully initialized [C66xx_0] [Core 0]: FFTC instance 1 successfully initialized [C66xx_0] Free descriptor queue 878 successfully setup. Descriptors allocated of type (2): 4 [C66xx_0] Free descriptor queue 878 successfully setup. Descriptors allocated of type (2): 4 A0=0x54 A1=0x0[C66xx_0] A2=0x0 A3=0xa[C66xx_0] A4=0x80034d A5=0xffffffff[C66xx_0] A6=0x8002f9 A7=0x0[C66xx_0] A8=0x0 A9=0x800ac7[C66xx_0] A10=0x54 A11=0x80082100[C66xx_0] A12=0x8002f9 A13=0x1[C66xx_0] A14=0x80085989 A15=0xa[C66xx_0] A16=0x0 A17=0x0[C66xx_0] A18=0x64 A19=0x64[C66xx_0] A20=0x6c A21=0x4c[C66xx_0] A22=0x0 A23=0x30[C66xx_0] A24=0x0 A25=0xc002f80[C66xx_0] A26=0x8009ac A27=0x8009ac[C66xx_0] A28=0x21f0600 A29=0x0[C66xx_0] A30=0x800d48 A31=0x0[C66xx_0] B0=0x1 B1=0x0[C66xx_0] B2=0x0 B3=0x80035a26[C66xx_0] B4=0xa B5=0x8008a6c4[C66xx_0] B6=0x4 B7=0x8008a664[C66xx_0] B8=0x0 B9=0xc00214c[C66xx_0] B10=0x800786cc B11=0x80036884[C66xx_0] B12=0x0 B13=0x80031468[C66xx_0] B14=0x8008a788 B15=0x800a20[C66xx_0] B16=0x0 B17=0x832fcc[C66xx_0] B18=0x40 B19=0x1e0[C66xx_0] B20=0x69 B21=0x10080ea0[C66xx_0] B22=0x40 B23=0x100816a0[C66xx_0] B24=0xc002144 B25=0x80000000[C66xx_0] B26=0xa01409 B27=0x0[C66xx_0] B28=0x0 B29=0xc002000[C66xx_0] B30=0xffffffff B31=0x800ac8[C66xx_0] NTSR=0x1000c[C66xx_0] ITSR=0x40c[C66xx_0] IRP=0x80037b0c[C66xx_0] SSR=0x0[C66xx_0] AMR=0x0[C66xx_0] RILC=0x0[C66xx_0] ILC=0x0[C66xx_0] Exception at 0x80039898[C66xx_0] EFR=0x40000002 NRP=0x80039898[C66xx_0] Internal exception: IERR=0x1[C66xx_0] Instruction fetch exception[C66xx_0] ti.sysbios.family.c64p.Exception: line 248: E_exceptionMin: pc = 0x80037b0c, sp = 0x00800a20.[C66xx_0] xdc.runtime.Error.raise: terminating execution
With default memory configurations of the test project, I'm able to execute it. Please somebody look in to the problem and help me in resolve the issue.
Thanks
You have a subtle problem that does not have an obvious solution. You have received advice and questions from three interested people. The broadly experienced BrandyJ gave you targeted advice for implementing your system, and you chose to follow some of that. The helpful and capable Faraday went so far as to load and run your project on the simulator, generating a question about your code's execution. I asked debugging questions twice, and I think it would be rude of me to ask you a third time without getting any response.
We all have different ways of debugging. Some see things that can change, then test whether changing those helps the problem. Some try to dig deeply into the symptoms to find the cause, and then make a targeted change to solve it.
My apologies that I am not in a position to debug your program for you. You are in very capable hands with the other two and the rest of the forum. I will continue to monitor this thread in case you have the opportunity and interest in following the introspection path.
Kind regards,RandyP
I have solved the issue by modifying link.cmd file, now my project executing successfully. Thanks for all your suggestions and help.
Excellent work.
If you would, please post the updated link cmd file for future readers. And for our curiosity.