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C6000 Multicore DSP
Keystone Multicore Forum (C66, 66A, AM5)
Modify PCIe-Boot-Example Hello World to L2-RAM only (instead of DDR) don't work
I'm working with am TMDXEVM6678L EVM and a Linux system. I first tried the PCIe-BootExamples provided by the MCSDK and the Hello World as well as the POST example works fine.
So I tried to modify the Hello World example in this way that only the Local L2 RAM is used (like in the POST example) to get some experience for own projects. I imported the HelloWorld-Project from MCSDK and modified these things (see attachments):-changed the pcieboot_helloworld.cmd to use only L2-RAM-created *.h file (via btbl, ...) and checked it (Entry point is 0x83CC00, BootTable is loaded at 0x830000)-modified pciedemo.c to load the HelloWorld directly into L2-RAM and compiled it
Now starting pciedemo.ko with insmod works fine, but the application don't start correctly and don't gives any output to the UART. dmesg says the correct boot entry and that 0xD898 bytes are loaded.
Debugging the Core 0 with CCS I see that the bootTable is loaded correct at 0x830000, but the PC stands at 0x830E22. Checking the original HelloWorld application, the PC is standing in the while-Loop at 0x....E964 or something so I think the PC hung up somewhere...
Have I forgotten something for the adaption from DDR to L2-RAM? How can I debug this further as there are no modifications to the program itself but only to the cmd-file and resulting bootTable (which seems okay)?
Be careful that the PCIe boot is done through IBL and it also executed form L2. If you overwite your code in that space, it might not work. I believe that the document should let you know where they are loading. If not, please let me know and I can get you the information.
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I've read this in the manual and I don't think that this is the problem. IBL uses memory from 0x800000 to 0x81BDFF, RBL uses 0x872DC0 to 0x87FFFF.
My bootTable is written to 0x830000, bootEntry is at 0x83CC00 so there should be no problem.
Can you load the symbols when you are chekcing through CCS. It will show you where in the code you are stuck. that might give us some clue.
Load the same .out file after selecting load symbol instead of "load program".
after some debugging with loading the symbols, I've seen that the code stucks here:
-main: write_uart (Line 152, then 118)-\pdk_C6678_1_0_0_21\packages\ti\platform\evmc6678l\platform_lib\src\platform.c: platform_delaycycles (Line 719)-here the code loops endless because the register TSCL always is zero in method CSL_chipReadTSCL()
I'm not sure why this happens as I only redefine some mapping of the code into the LocalSRAM as you can see in the attachment above.
Do you have an idea to this topic?
Could you try to add a write to the TSCL before the platform_uart_init(); in main of pcieboot_helloworld.c like that:
oldTSCL = CSL_chipWriteTSCL (0);Just in case the TSCL is not running yet ...Kind regards,one and zero
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Did the solution from one and zero worked for you?
sorry for the delay due to holiday. Yes, the solution from one and zero works perfect. I'm not sure why the TSCL is not running using the same boot example only with L2 cache instead of DDR, but now it works.
Thanks for your advice!
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