Hi,
I am having an issue reading specific parts of core0 L2 SRAM via my PCIe driver. I have a little usermode device memory reading application which works as follows:
vpu_read <dsp addr> <length>
which calls the driver to read <length> bytes starting at <dsp_addr>. The utility outputs the bytes read to stdout. My driver determines what area of the DSP memory is to be read, and 'reconfigures' the IB address translation of PCIe BAR1 to target that area. Everything works fine, except when accessing particular addresses of core0's L2 SRAM. Other Core's L2 SRAM can be accessed fine. for example:
vpu_read 0x11804330 4 > out
vpu_read 0x21804330 4 > out
vpu_read 0x31804330 4 > out
...
All these work correctly, however, the following:
vpu_read 0x10804330 4 > out
gives me:
Precise External Abort on non-linefetch (0x1028) at 0xcf800030
(0xcf800000 is the kernel virtual address for the start of BAR1, bar 1 has been mapped to 0x10804300 here).
After this occurs, I look at 0x01846004 via JTAG (which is L2EDSTAT) and see that the bit corresponding to "Parity error occurred during DMA access" has been set.
I know this seems like a long shot, but this has me stumped. Any ideas?
Thanks,
Joel
Joel,
Have you checked the data to compare what it is vs what it should be? Have you reset the device and does the issue persist?
Best Regards,
Chad
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Hi Chad,
Yes, when the read succeeds, the data looks correct. When the external abort occurs, I don't get any data to read. The issue persists across resets. I really appreciate any help with this one.
-Joel
Can you provide a dump of what the MPU registers have in them?
MPU0 Revision_Register 0x4E814901 Memory Mapped Configuration_Register 0x00000001 Memory Mapped Interrupt_Raw_Status_Set_Register 0x00000000 Memory Mapped Interrupt_Enabled_Status_Clear_Register 0x00000000 Memory Mapped Interrupt_Enable_Register 0x00000000 Memory Mapped Interrupt_Enable_Clear_Register 0x00000000 Memory Mapped EOI_Register 0x00000000 Memory Mapped Interrupt_Vector_Register 0x00000000 Memory Mapped Fixed_Start_Address_Register 0x00000000 Memory Mapped Fixed_End_Address_Register 0x00000000 Memory Mapped Fixed_MPPA_Register 0x00000000 Memory Mapped Programmable_Start_Address_Register 0x01D00000 (1 of 16, stride 16) [Memory Mapped] Programmable_End_Address_Register 0x01D803FF (1 of 16, stride 16) [Memory Mapped] Programmable_MPPA_Register 0x03FFFCB6 (1 of 16, stride 16) [Memory Mapped] Fault_Address_Register 0x00000000 Memory Mapped Fault_Status_Register 0x00000000 Memory Mapped Fault_Clear_Register 0x00000000 Memory Mapped MPU1 Revision_Register 0x4E814901 Memory Mapped Configuration_Register 0x00050001 Memory Mapped Interrupt_Raw_Status_Set_Register 0x00000000 Memory Mapped Interrupt_Enabled_Status_Clear_Register 0x00000000 Memory Mapped Interrupt_Enable_Register 0x00000000 Memory Mapped Interrupt_Enable_Clear_Register 0x00000000 Memory Mapped EOI_Register 0x00000000 Memory Mapped Interrupt_Vector_Register 0x00000000 Memory Mapped Fixed_Start_Address_Register 0x00000000 Memory Mapped Fixed_End_Address_Register 0x00000000 Memory Mapped Fixed_MPPA_Register 0x00000000 Memory Mapped Programmable_Start_Address_Register 0x34000000 (1 of 16, stride 16) [Memory Mapped] Programmable_End_Address_Register 0x3401FFFF (1 of 16, stride 16) [Memory Mapped] Programmable_MPPA_Register 0x03FFFC80 (1 of 16, stride 16) [Memory Mapped] Fault_Address_Register 0x00000000 Memory Mapped Fault_Status_Register 0x00000000 Memory Mapped Fault_Clear_Register 0x00000000 Memory Mapped MPU2 Revision_Register 0x4E814901 Memory Mapped Configuration_Register 0x00000001 Memory Mapped Interrupt_Raw_Status_Set_Register 0x00000000 Memory Mapped Interrupt_Enabled_Status_Clear_Register 0x00000000 Memory Mapped Interrupt_Enable_Register 0x00000000 Memory Mapped Interrupt_Enable_Clear_Register 0x00000000 Memory Mapped EOI_Register 0x00000000 Memory Mapped Interrupt_Vector_Register 0x00000000 Memory Mapped Fixed_Start_Address_Register 0x00000000 Memory Mapped Fixed_End_Address_Register 0x00000000 Memory Mapped Fixed_MPPA_Register 0x00000000 Memory Mapped Programmable_Start_Address_Register 0x02A00000 (1 of 16, stride 16) [Memory Mapped] Programmable_End_Address_Register 0x02A1FFFF (1 of 16, stride 16) [Memory Mapped] Programmable_MPPA_Register 0x03FFFCE4 (1 of 16, stride 16) [Memory Mapped] Fault_Address_Register 0x00000000 Memory Mapped Fault_Status_Register 0x00000000 Memory Mapped Fault_Clear_Register 0x00000000 Memory Mapped MPU3 Revision_Register 0x4E814901 Memory Mapped Configuration_Register 0x00010001 Memory Mapped Interrupt_Raw_Status_Set_Register 0x00000000 Memory Mapped Interrupt_Enabled_Status_Clear_Register 0x00000000 Memory Mapped Interrupt_Enable_Register 0x00000000 Memory Mapped Interrupt_Enable_Clear_Register 0x00000000 Memory Mapped EOI_Register 0x00000000 Memory Mapped Interrupt_Vector_Register 0x00000000 Memory Mapped Fixed_Start_Address_Register 0x00000000 Memory Mapped Fixed_End_Address_Register 0x00000000 Memory Mapped Fixed_MPPA_Register 0x00000000 Memory Mapped Programmable_Start_Address_Register 0x02640000 (1 of 16, stride 16) [Memory Mapped] Programmable_End_Address_Register 0x026407FF (1 of 16, stride 16) [Memory Mapped] Programmable_MPPA_Register 0x0003FCB6 (1 of 16, stride 16) [Memory Mapped] Fault_Address_Register 0x00000000 Memory Mapped Fault_Status_Register 0x00000000 Memory Mapped Fault_Clear_Register 0x00000000 Memory Mapped
Is the above what you need Chad? Thanks very much for your help!
For each of the MPU's are you saying that the Start Addresses, End Address and MPPA's for all 16 were the same for a given MPU#?
Unfortunately I've had to move on to a higher priority task for a bit. I will reply here when I get back to this issue. Thanks again for the help.