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Erick,

Which DSP are you using?

Generally, I have my GEL setup to do a GEL_Reset() whenever new code is loaded. This is a new system that I expect to restart everything it needs. You may find that useful for reasons such as this. It can be automated using a GEL function like OnFileLoaded.

It sounds like you are only using memset/memcpy equivalents. Is this correct? Does that mean you are only using QDMA. If that is the case, then it is a big puzzle ot me what could be causing your problem.

In any case, once you have done all of your initialization in main() and are just about to call BIOS_start(), go to the EDMA3 registers and look through them to see what might be set in the error registers or interrupt registers.

The most common problem is an extra event coming in without the code having re-loaded the PaRAM for a channel. To prevent this case, the easiest thing to do is to write 0xFFFFFFFF four (4) times to SECR and to SECRH and then write 0xFFFFFFFF once each to EMCR and EMCRH.

It also makes sense to clear IPR, which may be the source of the problem in your case.

Regards,
RandyP

SER x 4 then EMR

I'd also suggest taking a look at the SER (Secondary Event Registers) to make sure they aren't set.  They could have been set but not yet cleared from the existing running code when you stop and reload the new code.  The incoming events that are already set within the SER will not trigger the EDMA transfer until after the SER for the given event has been cleared. 

Best Regards,

Chad

Thanks for the suggestions, but I'm still having the same issue, I'm using a 6670 Rev 2.0.

I wasn't quite clear on what was happening, but the transfer (memset/memcpy) I call first when a code reload happens, does work completely, however it does not trigger the CSL_INTC0_CPU_2_EDMACC_GINT event (or at least the flag never gets set).  The complete copy or set works (with all the links and chaining) however when it is complete, no interrupt fires.  Again, works fine on a System Reset or power cycle.

I should mention also that I've done a GEL file reset (taken from the EVM RESET code) and it still does not work, only a "System Reset" gets it back into a state that it works again.

After looking a bit more into it, the first run (after reload) does trigger the CSL_INTC0_CPU_2_EDMACC_ERRINT event, not sure what the error is though, could someone point me in the right direction as to where to find what the error is?

Have you looked at the Interrupt registers to see if the event has been set but not processed,   A quick test is to trigger this event manually and see if the interrupt gets taken, if it doesn't then you need to track down what needs to be cleared out.

-Chad

If I trigger the system event (CSL_INTC0_CPU_2_EDMACC_GINT) manually, the interrupt fires, and then the rest of the transfers work.

After looking at IPR, bit 1 seems to always be set, the system reset seems to be the only way it is cleared, calling the 

CSL_edma3HwControl((CSL_Edma3Handle)gDmaHModule, CSL_EDMA3_CMD_INTRPEND_CLEAR, &regionIntr);

function is not clearing the bit (after calling CSL_edma3GetHwStatus((CSL_Edma3Handle)gDmaHModule, CSL_EDMA3_QUERY_INTRPEND, &regionIntr);), I've also tried writing a 1 to the ICR register but that also does not seem to clear it.

Any more insight into this?

Erick

Erick,

Are your regions setup correctly?

If IPR bit 1 is the relevant bit, you need to write a 2 to the ICR register to clear IPR bit 1. Try this also in the Expressions or Variables Window using CCS.

Regards,
RandyP