TI E2E Community
Digital Signal Processors (DSP)
C6000 Multicore DSP
Keystone Multicore Forum (C66, 66A, AM5)
c6657 Clock Requirements
Must a customer use CDCE62005 if they are not using PCI, SRIO, and MCM/hyperlink? How are those pins handled? No connect or tied high/low/Gnd?
They do require ENET, does this mean they need the shared clock with SRIO?
Given above subset of interfaces to be used, is there a simpler/smaller clock we recommend? Do they need jitter cleaning?
The use of the CDCE62005 is not required but it does meet the jitter specification for C6657. If the customer is using the Ethernet interface they will still need clocks for the CORECLK, the DDRCLK and the SRIOSGMIICLK. The later is used by the Ethernet interface and must be present. While I know of a two output clock generator in the same family as the CDCE62005, I am not familiar with a three output version of the device. If they pick a different device they will have to compare the jitter with the requirements provided in the hardware design guide. The clocks must meet these specifications for proper operation.
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