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  • Resolved

TMS320C6678: DDR3 configuration error on warm reset

Part Number: TMS320C6678

Hi

We recently updated the DDR3 RAM on our design from ISSI model IS43TR16128A to model IS43TR16128C because of obsolescence issues (they have the same specifications).

The DDR3 runs at 1333MHz and the old model "A" had no problems to correctly initialize.

The new model "C" however has a problem to re-configure the DDR3 memory after a warm restart. The first time the memory is configured it works fine. (It also works fine if it gets configured via a GEL file from CCS).

On a warm restart we also have active the PLL_REINIT_WORKAROUND in the IBL. In this scenario the PLLs get reconfigured before the DDR controller is reconfigured.

In this scenario the partial automatic leveling fails and the DDR_STATUS register returns 0x40000064, which indicates that the read DQS gate training and read data eye training timed out.

When the DDR3 PLL is lowered to operate at 1066MHz, the model "C" also start to work correctly without any errors.

We would like the DDR3 RAM to reliably operate at 1333MHz and not need to fall back to 1066MHz.

Do you any have advice for where to look for a solution?

Should we look at the leveling initialization values or is there some issue with re-configuring the PLLs before doing the DDR3 configuration?

Is there a method to hard reset the DDR3 memory controller and DDR3 RAM from software so that after the PLLs are configured the memory controller can be completely restarted?

  • Hi,

    We're looking into this. Feedback will be posted directly here.

    Best Regards,
    Yordan

     


     Please make sure you read the forum guidelines first.

  • In reply to Yordan Kovachev:

    Leon,

    I cannot think of a cause for the behavior that you are seeing.  I can only speculate that their is some marginality in your design that has now appeared when using the faster devices.  I recommend that you first recheck the design validation steps that would have been done when the board design was first commissioned with DDR3.  The steps are summarized on the following Wiki page:

    Tom

     

  • In reply to Tom Johnson 16214:

    post edited to fix link

     

  • In reply to Tom Johnson 16214:

    Hi

    Thanks for the reply.

    We already did recheck the validation steps, but it didn't improve operation.

    We will use the fallback option to 1066MHz for now.

    Regards,

    Leon

  • In reply to Leon Theunissen:

    Leon,

    Please post your completed PHY_CALC and REG_CALC worksheets for review.  Also, please post your report showing that the length matching rules were met.

    Tom

     

  • In reply to Tom Johnson 16214:

    Leon,

    I have not seen a response for 2 weeks.  Can I close this ticket?

    Tom

     

  • In reply to Tom Johnson 16214:

    Hi

    Sorry for not responding earlier, everyone here is still on leave at the moment.

    I hope to get the information you require during next week.

    Regards,

    Leon

  • In reply to Leon Theunissen:

    Hi Tom

    Please find attached the two worksheets for 667 MHz.

    Some of the DQS lines are marginal, but what does not make sense to us is the fact that:

    - The DDR3 configures correctly the the GEL file @ 667 MHz

    - The DDR3 configures correctly after power-on @ 667 MHz 

    Are we missing something?

    Please advise

    Kind regards

    Piet

    8080.DDR3 PHY Calc v11.xlsx1411.DDR3 Register Calc v4.xlsx

  • In reply to Piet Du Toit:

    Piet,

    I cannot draw conclusions from just the REG_CALC sheets.  I need to receive the length matching report and the PHY CALC sheets as well.

    Tom

     

  • In reply to Tom Johnson 16214:

    Hi Tom

    Both files are uploaded.

    Regards

    Piet

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