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  • TI Thinks Resolved

CCS/TMS320C6655: Fail to connect the c6655 to PC by pcie

Part Number: TMS320C6655

Tool/software: Code Composer Studio

Hi TI engineer:

     We have a C6655 board, which have a pcie port to be put in pcie slot of the PC Motherboard. We put the board in the slot and make sure that connection is good. The we load a program to init the pcie port.But the program stuck at here:

     

     We check the register status of debug0:

      

      It shows that the ltssm_state is not in L0.So link trainning isn't made through.

      We try a full reset, but it doesn't make any difference.The connection can't be built.

      Software environment: CCS 5.5+bios_mcsdk_02_01_02_06

      The program used to init the pcie have been attached. So does the gel we use to init the pll and ddr 

      Could you help us on how to solve this problem? How to make c6655 connect to PC? Thank you very much.DSP_C665x.gelCould you give us some g

PCIe_EndPoint_PC.rar

      

  • The team is notified. They will post their feedback directly here.

    BR
    Tsvetolin Shulev
  • Can you indicate if this is a custom board or TI EVM that you are using ? Are you using the PCIe example in MCSDK ? If this is custom board, have you checkout this setup on the TI EVM. Do you have an I2C EEPROM based IBL that performs PCIE init.

    Have you checked the debug steps indicated in the PCIE FAQ :
    processors.wiki.ti.com/.../PCI_Express_(PCIe)_Resource_Wiki_for_Keystone_Devices

    Please refer to the section A.1 in PCIe user guide for the LTSSM state decoding. And are you trying the C6678 PCIe LLD example on C6678 device please? By default, the LLD example configures the C6678 PCIe as x1 Gen1.

    Regards,
    Rahul

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  • In reply to Rahul Prabhu:

    Hi Rahul
    What we use is not a TI EVM,but a EVM board provided by GuangZhou Tronlong, one of the famous embedded integrated solution provider in China.
    We can make sure that PCIE init has been executed, because most of the import register of Pcie has been set,such like Command Status Register.
    Beyond that,we find some description about this ,in section 2.2 of Peripheral Component Interconnect Express (PCIe):
    Many PCIe connections, especially backplane connections, require a synchronous
    reference clock between the two link partners. To achieve this a common clock source,
    referred to as REFCLK in the PCI Express Card Electromechanical Specification,
    should be used by both ends of the PCIe link. If Spread Spectrum Clocking (SSC) is
    used it is required that a common reference clock be used by the link partners.
    It seems like we should to set common clock to make C6655 share the clock with PC board?Do you think it's the key? Thank you very much.
  • In reply to YUCHAO WANG:

    Hi,

    When you tried to use a host PC to enumerate a C665x DSP card, the typical issue is that PC uses a SSC clock to reduce the EMI, the PCIE reference clock varying around 100MHz. The C665x card has a fixed 100MHz PCIE reference clock. From our past experience, the PCIE enumeration always failed. You need have a common reference clock for both (let the host PC sourcing its PCIE ref clock to DSP card).

    TI have C6678 EVM, there is a switch pin setting to let the C6678 either using the PCIE local clock or from an external source. We used that for PCIE testing with a host PC.

    Regards, Eric

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