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TMS320C6678: SRIO RX PBRS Pattern verify

Part Number: TMS320C6678

Hi,

 

We are using a TMS320C6678 DSP connected by SRIO (Port 2 only) to a Kintex Ultrascale FGPA. The link is configured as 1x @5.0Gb/s.

SRIO reference clock to DSP and SRIO reference clock to FPGA are coming from the same clock source.

 

We want to test (and tune) our SRIO Link with PRBS7 patterns transmitted between the FPGA and DSP. Our FPGA is able to transmit PRBS7 through its Tx port and verify PRBS7 data on its Rx Port. (IBERT design type).

 

On the other side, our concern is how to activate the DSP ‘PRBS7 features that seem to exist both at DSP’ Rx side and DSP’ Tx side

For example we have initialized @(0x02620374) = 0x04440485, and @(0x02620378) = 0x001E8015 in order to define the testpattern as ‘PRBS7’

In that configuration the FPGA recognizes the pattern without any error.

But on the DSP side , it is not clear which register/bit to look at.

We observed the  SRIO_SERDES_STS register (0x02620154).bit15 but it is not stable : OK for 1 second, then NOK for 1 second, and so on…

At the contrary if we switch the FPGA TX pattern to another PRBS type, then  SRIO_SERDES_STS.bit15 remains stable NOK.

 

Hence the questions:

-       Are the above register initialization enough for our test ?

-       Then, how to correctly configure the DSP RX side to check/verify PRBS patterns ? What are the register involved here ?

-       Which REGISTER.bit gives the OK/NOK result ?

 

Nota : We also tried to configure the DSP in loopback mode using @(0x0291 B180).bit23 = 1, but as explained in the Errata Advisory 17, the link is not stable and some data are corrupted

 

Thank you for your help,

 

Regards,

Yohann

 

  • Hi Yohann,

    How are the SRIO_SERDES_CFGRX and SERDES_CFGTXn_CNTL? Check bit field [25-23] TESTPATTERN, as far as I understand it should be set to 010b -> PRBS7 test pattern.

    Best Regards,
    Yordan

     


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  • In reply to Yordan Kovachev:

    Hi Yordan,
    As indicated in my request, the following register are configured as :

    SRIO_SERDES_CFGRX2 (address 0x02620374)  = 04440485 :  <Bit 27-25> : 0b 010
    SRIO_SERDES_CFGTX2_CNTL (address 0x02620378)  = 0x001E8015  :  <Bit 25-23> : 0b 000

    We've also tried to set the SRIO_SERDES_CFGTX2_CNTL = 0x011E8015 (<Bit 25-23> : 0b 000) but it does not affect the Rx Driver.

    Best Regards,

    Yohann

  • In reply to user5200299:

    Hi Yohann,

    Let me check further. I will update as soon as I have some feedback.

    Best Regards,
    Yordan

     


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  • In reply to Yordan Kovachev:

    Hi,

    Besides the SRIO user Guide. I think you should also check the SERDES Link Commission on Keystone I and II Devices:
    www.ti.com/.../sprac37.pdf

    See Section 2.2 PRBS Test for the correct steps that need to be taken in order to execute adequate PRBS test.

    Best Regards,
    Yordan

     


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  • In reply to Yordan Kovachev:

    This documentation have a lot of information, but all the tests available in the SDK seems to be only present on the components based on Keystone II SDK. I didn't manage to find these tests in the 6678 SDK (Keystone I).

    Therefore the question remains intact, how can I check that the DSP receives a PRBS7 frame well ?

  • In reply to user5200299:

    Hi,

    This documentation have a lot of information, but all the tests available in the SDK seems to be only present on the components based on Keystone II SDK. I didn't manage to find these tests in the 6678 SDK (Keystone I).


    The code should be similar for Keystone I devices (they share similar SDK RTOS and SRIO/SERDES interfaces). Try adapting the tests for your KS1 device and it should work.

    Best Regards,
    Yordan

     


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