TMS320C6670: The problem with running the same projects in two cores

Part Number: TMS320C6670

My device is TMS320C6670.







I am trying to run the same project in two cores while one core runs NDK part and another core runs FFTC part.  But I have a hard time making two cores run the corresponding part separately. 

I use the following function in my project to distinguish the coreNum. 


coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);

core0 runs the following part :

/* Get information about the platform so we can use it in various places */
memset( (void *) &gPlatformInfo, 0, sizeof(platform_info));
(void) platform_get_info(&gPlatformInfo);

(void) platform_uart_init();
(void) platform_uart_set_baudrate(115200);
(void) platform_write_configure(PLATFORM_WRITE_ALL);
/* Clear the state of the User LEDs to OFF */
for (i=0; i < gPlatformInfo.led[PLATFORM_USER_LED_CLASS].count; i++) {
if (system_init (coreNum, fftcInstNum) != 0)
System_printf ("[Core %d]: FFTC Example system init failed \n", coreNum);
/* Setup cppi descriptors and PA . */
cppi_cfg.dma_num = Cppi_CpDma_PASS_CPDMA;
cppi_cfg.num_tx_queues = NUM_PA_TX_QUEUES;
cppi_cfg.num_rx_channels = NUM_PA_RX_CHANNELS;
if (res_mgr_init_cppi (&cppi_cfg) != 0)
platform_write ("Failed to initialize CPPI subsystem \n");
platform_write ("CPPI successfully initialized \n");

if (res_mgr_init_pass(&qmss_cfg)!= 0) {
platform_write ("Failed to initialize the Packet Accelerator \n");
platform_write ("PA successfully initialized \n");

bIsSysInitDone = 1;

/* Writeback L1D */
CACHE_wbL1d ((void *) &bIsSysInitDone, 4, CACHE_WAIT);

core1 runs the following part :

System_printf ("[Core %d]: Waiting for Sys Init to be completed ... \n", coreNum);
CACHE_invL1d ((void *) &bIsSysInitDone, 4, CACHE_WAIT);
} while (bIsSysInitDone == 0);
/* Start Queue manager on this core */
Qmss_start ();


The problem is that only core0 gets to run it's own part and core1 seems to get stuck in somewhere.  I tried to change the highlighted part(with red color) to coreNum==1, and core0 results in running the else part and core1 still ended up getting stuck. 

Please help me with this and I'd like to express my sincere gratitude in advance.

And my .cfg file is attached. 


1 Reply

  • Hi Button :-)

    to create the same firmware for all cores you must do the following things:

    • keep sure that all code (.text) is places in shared memory
    • keep sure that the _c_int00 is placed on a address multiple 0x400, which is needed to start the secondary cores by master core #0
    • keep sure that all data sections are placed in the right local and/or shared memory, also for SYS/BIOS related data
    • add code for master core #0 to start the secondary cores.

    The list will be not complete. Keep in your mind, that the Rom Boot Loader RBL is only able to load the code and data for the master core. After them the master core will be started. The secondary cores are waiting for a boot command via IPC interrupt, e.g. look here:

    Kind regards