• Resolved

TMS320C6678: RapidIO to a Cyclone IV fpga

Part Number: TMS320C6678

Dear Mr./Ms.,

Cyclone IV GX fpga's RapidIO IP core runs as a slave with a DSP 6678, direct connect.

Run in 1X mode , 2.5GHz.

In FPGA qsys, rapidio ip core has only io_write_master and io_read_master connecting to a DPRAM. No cpu, no Nios.

Now, Port_OK while fpga get no io_m_wr_write or io_m__rd_read signal when DSP NWRITE/NREAD/SWRITE.

DSP side can sucessfully write and read by rapidio in internal loop mode.

Could you please give me some suggestion on how to debug it?

Thank you.