Keystone Multicore Forum (C66, 66A, AM5) - Recent Threads

A few questions about interruptions

Clement Mesnier — Mon, 13 May 2013 15:20:36 GMT

Hello all,

I'm doing some preliminary work on interruptions for the DSP C6678.
As I read the documentation (user guides, wiki, chm doc) I run into some questions :

- when you say "host" does it mean the DSP (all 8 cores) or the corepac (1 core) ?
- what does the acronym GEM mean ?

I have identified 4 ways to disable/restore interruptions on a single core, which are :
1) assembly (DINT, RINT)
2) intrinsics (_disable_interrupts, ...)
3) CSL (CSL_intcGlobalDisable, ...)
4) Sysbios HWI (Hwi_disable, ...)

For the DSP level (all 8 cores at once) would it work using :
a) CSL : CSL_CPINTC_enableAllHostInterrupt(cphnd);
or b) Sysbios : CpIntc_disableAllHostInts(UInt id);?

If I disable the 4 CICs then I won't get any events/interruptions right ? (for all cores I mean)
Is there any simpler way ?

Thank you,
Clément

Keystone Bootloader: RBL DDR3 configuration. Leveling?

Ricardo Martinez — Mon, 13 May 2013 08:14:10 GMT

Dear all,

I'm using C6670 EVM. I'm loading my application into DDR3 using Ethernet RBL (ROM Boot Loader). I am not using I2C Intermediate Boot Loader.. So, my board is properly configured for Ethernet boot and everything works as expected.

However, I'm worried about the following: DDR3 configuration by RBL does not include leveling configuration (read or write leveling). I have checked this in Table 2-3 "DDR configuration" in Keystone Architecture Bootloader User Guide (SPRUGY5B). RBL writes into DDR3 PLL configuration, SDRAM Config Register, Timing, PHY CTL, etc, but not into Leveling configuration.

Without leveling configuration, I think that RBL access to DDR3 might not be reliable. One easy solution for this would be slowering down DDR3 clock frequency by PLL configuration. Slow access to DDR3 might not need leveling. However, when I configure DDR3 PLL to 400MHz (this means DDR3-800 access, while default configuration for EVMC6670 is DDR3-1333), RBL can't write to DDR3. So my application won't work. Any DDR3 PLL frequency below default configuration (666.67MHz) won't work. I am updating also timing parameters for the new frequency values without success.

I'm writting the following boot table section into my application binary.

00 00 00 70 00 8F 35 00 02 42 80 F5 00 00 00 00 00 00 00 14 00 00 00 02
63 06 2A 32 00 00 00 00 00 00 14 50 11 13 78 3C 30 71 7F E3 55 9F 86 AF
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 70 07 32 14 00 00 00 00 00 10 01 0F 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

According to "tiboot_c66x.h" (because Table 2-3 in SPRUGY5B has an errata), those 3 words in bold above are for DDR3 PLL configuration. That configuration above works perfectly (again, without leveling so I don't truts it to work 100% of the booting processes). 0x14 == 20 (multiplier). 0x2 (dividier). 66.67MHz x 20 / 2 = 666.67MHz appropiate for DDR3-1333 operation.

Changing DDR3 configuration into DDR3-800 (400MHz clk):

00 00 00 70 00 8F 35 00 02 42 80 F5 00 00 00 00 00 00 00 0C 00 00 00 02
63 06 2A 32 00 00 00 00 00 00 14 50 11 13 78 3C 30 71 7F E3 55 9F 86 AF
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 70 07 32 14 00 00 00 00 00 10 01 0F 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Above configuration won't work.

Please note that I can configure DDR3 PLL to 400MHz with Emulator editing GEL files and it works properly.

To summarize:

1) I'm worried about lack of DDR3 leveling configuration in RBL

2) I don't understand why I can't configure DDR3 PLL to 400MHz using RBL (indeed, any value below 666.67MHz won't work). I think this could be a feasible solution for the problem in 1).

Thanks in advance.

Regards,

Ricardo

C6678 MSMCSRAM setting ?

Stellar Respree — Mon, 20 May 2013 12:15:27 GMT

As for TI6678 memory map, MSMCSRAM area is 0x0c00_0000 - 0x0c3f_ffff.

And I want to reduce MSMCSRAM 0x0c00_0000 - 0x0c1f_ffff and use 0x0c20_0000 - 0x0c3f_ffff exclusive.

The reason for this setting is I want to use upper half of MSMCSRAM area for PCIe DMA area (for my own application)

and I do not want QMSS or CPPI or another shared resource collide with my DMA data.

So my question is:

1. Could this be a accaptable approach? (devide MSMCSRAM area) ?

2. How can I change MSMCSRAM area to 0x0c00_0000 - 0x0c1f_ffff ?

Regards,
Stellar

C6678 Jpeg Encoder DRI Marker

qbliu — Fri, 29 Mar 2013 03:02:52 GMT

Hi, everyone:

I use the C6678 for jpeg encoder, the jpeg encoder codec version is C66x_jpegenc_02_02_00_01_ELF.

My question is when I encode the picture without the DRI Marker, the encode total time is about 80ms, while with the DRI Marker, the total time is about 300ms!!! When I change the DRI_Interval, it is also about 300ms!!!

Is it ture? (I am sure that the encoded jpeg picture is right, and the size of the picture with or without DRI Marker is almost the same.)

thanks a lot.

The value returned by RMAN_assignResources function is IRES_ENORESOURCE...

zhao sun — Mon, 17 Sep 2012 09:13:56 GMT

Hi,

I tried to initialize 2 or more H264 baseline video codec's instance in the same thread base on the h264 video encoder unit test program running on c6678.

The first instance can be create successfully while the value returned by RMAN_assignResources function of the second instance is IRES_ENORESOURCE.

So how can I assign the same EDMA resource to 2 or more instance in the same thread? The calling sequence is as below:

RMAN_init();

ires_status = RMAN_assignResources((IALG_Handle)codecHandle, (IRES_Fxns*)resFxns, scratchId); //Codec instance 1 return IRES_OK

ires_status = RMAN_assignResources((IALG_Handle)codecHandle, (IRES_Fxns*)resFxns, scratchId); //Codec instance 2 return IRES_ENORESOURCE ... ...

The codecHandle above are different and the resFxns are the same. The RTSC config is set below:

RMAN.useDSKT2 = true;

RMAN.yieldSamePriority = true;

RMAN.tableSize = 10;

RMAN.maxAlgs = 10;

That is I want to create 10 instance of the same algorithm in the same thread. So how can I do that?

Thanks a lot!

B.R.

Sunzhao

Unable to connect to TMDXEVM6670LE using CCS 5.0.1

Gowtham Nagaraj — Wed, 22 May 2013 13:18:20 GMT

Hi All,

I am working on TMDXEVM6670LE board and using CCS 5.0.1, i have made a sample application program which i compiled using the specified configuration files.I am using the onboard emulator XDS100, i have been using the standard gel files provided by the TI CC670l.gel, when i try to run my program i am not able to connect to target. I am getting error

Error connecting to the target:
Cannot access register at 0x00000000
(Error -2131) @ 0 (0x0)

When i try to connect to the target, i had referred through the discussions i configured the path of gel files correctly but still i am not able to connect to target.Could some one provide some information on whether i am missing something?

My current configuration is attached in mail.

I have another strange error in my linker.cmd file below is my source of linker.cmd

-heap 0x8000
-stack 0x1000
/*-l../../../lib/dsplib.a66 */
MEMORY
{
L2SRAM (RWX) : org = 0x800000, len = 0x80000
MSMCSRAM (RWX) : org = 0xc00000, len = 0x400000
DDR3 (RWX): org = 0x80000000, len = 0x10000000
}

SECTIONS
{
.text: load >> L2SRAM
.text:touch: load >> L2SRAM

GROUP (NEAR_DP)
{
.neardata
.rodata
.bss
} load > L2SRAM

.far: load >> L2SRAM
.fardata: load >> L2SRAM
.data: load >> L2SRAM
.switch: load >> L2SRAM
.stack: load > L2SRAM
.args: load > L2SRAM align = 0x4, fill = 0 {_argsize = 0x200; }
.sysmem: load > L2SRAM
.cinit: load > L2SRAM
.const: load > L2SRAM START(const_start) SIZE(const_size)
.pinit: load > L2SRAM
.cio: load >> L2SRAM
xdc.meta: load >> L2SRAM, type = COPY
}

When i try to build my program i am getting error

"../linker.cmd", line 44: error: L2SRAM memory range has already been
specified
"../linker.cmd", line 44: error: L2SRAM memory range overlaps existing memory
range L2SRAM
"../linker.cmd", line 45: error: MSMCSRAM memory range has already been
specified
"../linker.cmd", line 46: error: DDR3 memory range overlaps existing memory
range DDR2

Could you provide some inputs on this?

Regards

Gowtham

Proper Way to Benchmark Timing within OpenMP on C6678

Ryan Radjabi — Fri, 17 May 2013 01:31:29 GMT

What is the proper way to calculate execution times within a single core for a multi-core application using OpenMP?

In a single-core application, I use the Timestamp_get32() function to count cycles between lines of code, although this doesn't seem to return the correct value for code inside the #pragma omp parallel private(nthreads, tid) block in my code.

I ran the multiplication for a Hanning window both inside and outside the OMP pragma and roughly got the results I was seeing on my single-core application. Time benchmarks within the pragma are around 6-8 times what they are outside the pragma. Check out the simple C code below. There isn’t anything fancy going on, this is built around the HelloWorld template for OpenMP. This time difference is irrelevant if I set this application for 1 core, 4 cores, or 8 cores.

Can Timestamp_get32() be trusted within the pragma statement?

/******************************************************************************

* FILE: omp_hello.c

* DESCRIPTION:

* OpenMP Example - Hello World - C/C++ Version

* In this simple example, the master thread forks a parallel region.

* All threads in the team obtain their unique thread number and print it.

* The master thread only prints the total number of threads. Two OpenMP

* library routines are used to obtain the number of threads and each

* thread's number.

* AUTHOR: Blaise Barney 5/99

* LAST REVISED: 04/06/05

******************************************************************************/

#include <ti/omp/omp.h>

#include <string.h>

#include <assert.h>

#include <stdio.h>

#include <time.h>

#include <stdint.h>

#include <xdc/std.h>

#include <xdc/runtime/System.h>

#include <ti/sysbios/BIOS.h>

#include <xdc/runtime/Log.h>

#include <xdc/runtime/Timestamp.h>

#include <math.h>

#define NTHREADS 1

#define FFT_MAX_L 2048

#define PI 3.14159265358979323846

float multiplier[ 2048 ];

void generateHanningLookup( void )

{

int32_t i;

for (i = 0; i < 2048; i++)

{

// equation from stackoverflow.com

multiplier[ i ] = 0.5 * ( 1 - cos( 2 * PI * i / ( FFT_MAX_L - 1 ) ) );

}

void main()

{

int nthreads, tid;

nthreads = NTHREADS;

omp_set_num_threads(NTHREADS);

int16_t windowOutputData[ FFT_MAX_L ];

uint16_t j;

uint32_t start, totalTime;

generateHanningLookup();

start = Timestamp_get32();

for( j = 0; j < FFT_MAX_L; j++ )

{

windowOutputData[ j ] = j * multiplier[ j ];

}

printf( "HANNING#1 = [ %u ] cycles \n", ( Timestamp_get32() - start ) );

totalTime = Timestamp_get32();

/* Fork a team of threads giving them their own copies of variables */

#pragma omp parallel private(nthreads, tid)

{

/* Obtain thread number */

tid = omp_get_thread_num();

printf("Hello World from thread = %d\n", tid);

/* Only master thread does this */

if (tid == 0)

{

nthreads = omp_get_num_threads();

printf("Number of threads = %d\n", nthreads);

// Hanning Window

start = Timestamp_get32();

for( j = 0; j < FFT_MAX_L; j++ )

{

windowOutputData[ j ] = j * multiplier[ j ];

}

printf( "HANNING#OMP = [ %u ] cycles \n", ( Timestamp_get32() - start ) );

}

else

{

tid = omp_get_thread_num();

uint32_t startMp = Timestamp_get32();

for( j = 0; j < FFT_MAX_L; j++ )

{

windowOutputData[ j ] = j * multiplier[ j ];

}

printf( "HANNING#%u = [ %u ] cycles \n", tid, ( Timestamp_get32() - startMp ) );

}

} /* All threads join master thread and disband */

printf( "OMP TIME = [ %u ] cycles \n", ( Timestamp_get32() - totalTime ) );

start = Timestamp_get32();

for( j = 0; j < FFT_MAX_L; j++ )

{

windowOutputData[ j ] = j * multiplier[ j ];

}

printf( "HANNING#2 = [ %u ] cycles \n", ( Timestamp_get32() - start ) );

}

C6678 SRIO port error

Jason Gao — Fri, 24 May 2013 03:01:18 GMT

Hi All:
We have a design that C6678 and Xilinx Virtex6 FPGA connected together througn SRIO.
We do some test like this:
1、C6678 run a DDR3 test for about 10 minites for one time, C6678 sends and receives SRIO doorbells with FPGA.
2、 Then C6678 sends 32KB of packets to FPGA with a doorbell at last, FPGA receives the doorbell and sends the packets back.
3、 Repeat step1 and Step2.

We have a counter that counts the time of step1 and step2.
Each time when the value of counter reaches 0x5C, Some errors appear.

Bit2 and Bit17 of register SPn_ERR_STAT is not right.
Bit2 is set to 1: Port Error occurs.
Bit17 is set to 1: Output Error-encountered occurs.

Can anyone tell me what maybe the reason?
Thank you very much.

DSCP-8681E hangs host

Andrey Lisnevich — Fri, 04 Jan 2013 18:21:50 GMT

Hello,

I am working with DSCP-8681E and use Desktop Linux SDK, MPEG-2 and H.264 BP codecs for transcoding on multiple cores. I run separate instances of transcoder on all the cores but do not communicate between them (no IPC).

I noticed that codecs work much faster when their code (.text segment) is placed in MSMCSRAM memory (code was placed in dedicated to each core DDR segment before) so I am refactoring transcode program to place single code segment into MSMCSRAM and share it between all the cores.

But when I did the refactoring DSCP-8681E started to behave strange when I run transcode on 2 cores on one DSP.. On first run everything works correctly, transcoding goes on both cores. After soft reset (i.e. "dsp_utils reset..." command) and second run it may:

a) fail on one of cores with IRES_EFAIL while RMAN_activateAllResources

b) hang host PC with error:

Boot config words: 0x19, DSP Reset success !
pciedrv_driver: Error in ti667x_ep_init_bar, ib trans num 0!, ret = -2
pciedrv_driver: Found: IB_BAR = FFFFFFFF, IB_START_LO = FFFFFFFF, IB_START_HI = FFFFFFFF
pciedrv_driver: Expected: IB_BAR = 00000001, IB_START_LO = C1000000, IB_START_HI = 00000000.
pciedrv_driver: Error in ti667x_ep_setup_bar, ib trans num 0!, ret = -1
pciedrv_driver: Found: IB_BAR = FFFFFFFF, IB_OFFSET = FFFFFFFF.
pciedrv_driver: Expected: IB_BAR = 00000001, IB_OFFSET = 10800000.

c) it may just not start transcode program on DSP.

Then I need hard host reboot to successfully run transcoding on 2 cores again. It never runs transcode on both cores again without hard reboot.

I assume that because of refactoring something goes wrong with resource initialization (i.e. EDMA controller, etc.) but while the refactoring I didn't changed code that works with RMAN at all. That is why I am confused.

My questions are:

1) Do you know possible reasons of the RMAN failure and host hang?

2) Can you review app.cfg and transcode.map to find possible problems?

3) Is it correct to share .text and .cinit segments between cores?

4) Can I share other sections that has "r--" and "r-x" permissions between cores?

5) I noticed that .const section has "rw-" permissions. Why it is not "r--" if it contains constants? Can I share it between cores (i.e. place this section into MSMCSRAM)?

usage of both SGMII on EVM6678L problem

Kaka Huang — Fri, 24 May 2013 02:18:04 GMT

Hi, everyoe!

I have a project that must use the SGMII0 and SGMII1 for two Ethernet connection. But as the lib source files and user guide files shown, the default connection of SGMII and PHY is SGMII1, the SGMII0 is linking to AMC. Some people give an imperfect way to only use the SGMII0 (http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/226969/799906.aspx#799906). While my purpose is using the SGMII1 and SGMII0 simultaneously, so how can I reach the goal??

Additionally,

[1] if I build my project based on the exampleProject client , so, what should to do or should I pay attention to??

[2] The DSP send or receive data from SGMII0-PHY or SGMII1-PHY, how can the DSP distinguish which port should be operated？

My CCS is 5.2.1 and PDK is 1.0.0.18.

thanks for all!

Kaka Huang

2013/5/24

Using the ARM in TCI6638K2K on EVMK2HX

Barath Ramesh — Tue, 14 May 2013 21:01:38 GMT

Hi,

I was able to get the DSPs to work on the device (only single core) . I have a few questions about the device and the board

1) How do I compile code for Cortex A-15 using CCS i.e the linker command file for ARM and the device to be selected while making the project (TCI6638 seems to compile only for DSP)?

2) My OpenMP binaries that worked on TMS320C6678 do not execute on TCI6638 C66xx CorePac, am I doing anything wrong? Even the example OMP hello world project does not execute on the DSPs.

3) I currently use "Texas Instruments XDS2xx USB Onboard Emulator" instead of "Texas Instruments XDS2xx USB Emulator" as the later requires a license. Could this become an issue later on in my multicore development?

Thank you in advance.

Best regards,

Barath Ramesh

BAR0 not visible from RC

aymeric dupont — Wed, 15 May 2013 05:32:11 GMT

Dear support,

I hope you can help me with this very strange issue that we are experiencing. I am not sure if I should classify my problemas a Boot Issue or Pcie Issue.

The RBL enables the C6670 to boot from PCIe. However, the default window size are too big for our host to allocate memory and access all the bars.

Because of this problem, we created our own IBL based on the code provided by TI in the function iblPCIeWorkaround from mcsdk_2_01_00_03\tools\boot_loader\ibl\src\device\c66x\.

For the last 2 month, we have been using successfully a bootstrap that starts the RBL in from SPI in CS1, retreives our IBL from flash memory, runs the IBL and we can see our board on the pcie bus with 5 bars from a linux host. (if you need I can provide the detail lspci command)
When looking at this command we can identify 5 BARS that are configured as our IBL set them up.

BAR0: 32k
BAR1,2,3: 1M
BAR4: 4M

We are updating our boot process to boot from EEPROM. We changed the boot strap. Since it is the same code, we just regenerated the binary file (updating the parameter passed to romparse.exe) and we store it in EEPROM. We did not change one line of the source code of our working IBL

For the last week we have beleived that the board was booting properly as we did not really need to do any memory/register access via the host. Moreover, the linux host sees the board (lspci) and updates the BAR registers (0x21800000+0x1010) on the EP.

However, we started to have strange issues reading and writing memory regions on the DSP from the host.
We we looked a bit further, lspci -x -v here was our surprise:
BAR1,2,3: 1M
BAR4: 4M

BAR0 has disapeared. According to you manual, BAR0 is the only bar that can be used to access the pcie registers. We spent a lot of time investigating and we narrow it down to:

Once the RBL boots from flash => all is good

Once the RBL boots from EEPROM (same problem for eeprom @0x50 or eeprom @0x51) => Not good

I can provide you the source code of the IBL under NDA if you need but perhpas you have an idea of what is going on or perhpas you have heard of such a problem.

Is there additional settings required in the IBL when booting from i2c that I do not require when I boot from SPI

Thanks in advance

Aymeric

Timer cycles gets divided by 8 without main PLL Init

Sudarshan R — Thu, 23 May 2013 12:24:26 GMT

Hi all,

We are using timer to generate ticks for a specific application. We find that the timer cycles/timer profile value is getting divided by 8 to the actual value what we must get. Is it because the internal clock for timer = CPU clock/8??
However, after doing the main PLL initialization, we are getting the expected timer profile value. So, what might be the reason why the timer value got divided by 8 without the main PLL initialized. ?? Had glanced the Timer User Guide but couldn't find any clue there. Any brief explanation would be really helpful.

Regards

Sud

Measuring execution time Cortex-A15 of TCI6638

Barath Ramesh — Thu, 23 May 2013 12:22:41 GMT

Hi,

How do I measure the execution time of my code running in the ARM Cortex-A15 of TCI6638? I use TSCH/TSC for C6678 but is there a similar set up available for ARM in order to measure the execution time?

Thank you in advance.

regards,

Barath Ramesh

SmartReflex for TMS320C6657CZH25

Mina — Tue, 14 May 2013 09:35:52 GMT

Hi,

We are using TMS320C6657CZH25 and TMS320C6657CZH with LM10011SD.

Both TMS320C6657CZH25 and TMS320C6657CZH output 6-bit VCNTL signals by the reset release after the sequence of the power supplies in our board.

These VCNTL signals are corresponding to VCNTL value of register 0x02350014 in bit 21 to 16.

The value of register 0x02350014 in TMS320C6657CZH25 is 0x0FFF0000. This is same value in every TMS320C6657CZH25.

In TMS320C6657CZH, the value is different in every device. One of them is 0x07DF0000.

CVDD for TMS320C6657CZH is controlled to about 0.9V. But CVDD for TMS320C6657CZH25 is 1.1V, It doesn't change from an initial voltage.

Power consumption of TMS320C6657CZH is from beginning to end steady.

It of TMS320C6657CZH25 keeps increasing depending at the own temperature. It is saturated with about 6-watt.

We think that we have appropriately cooled it.

1. Do we keep using TMS320C6657CZH25 in CVDD is 1.1V?

2. How much is appropriate power consumption of TMS320C6657CZH25?

3. Should I control CVDD for TMS320C6657CZH25?

My best regards.

PLL Initialization

Leo Girault — Thu, 23 May 2013 09:19:18 GMT

Hi,

I'm using a TMS320C6678-EVM board and I've some issue : I need to load a program on several cores and I've noticed when I load the program on cores 1...7 (not core 0), the PLL doesn't seem to work correctly after several executions (program works slowly, some peripherals are unable to work, a "Trouble Reading Memory Block" message appears, ..).

When I connect the core 0 (without loading something), the problem disappears, because the PLL is initialized during execution of the GEL file (I'm using the default GEL file evmc6678l.gel). On this GEL file, it appears that only core 0 can initialize PLL (line 852 : "// Only core 0 can set these"). Is that true ? I thought that cores were independants...

I tried to comment lines where the condition "if (DNUM == 0)" appears and lauch this GEL file on core 1 only and it seems to work properly, but I would like to be sure that I can do it.

Does anyone can answer me ?

Thank you for your time.

L.G

Configuration :

MCSDK 2.1.2.6 - CCS 5.3.0.0009 - PDK 1.1.2.6

FPGA to boot-up the C6678 Abut SRIO and clock??

dana tu — Mon, 17 Oct 2011 04:18:09 GMT

In our design, we would like to use the FPGA to boot-up the DSP. As we would provide a single 4x lane SRIO communication link (3.125Gbps) for them, we want to use SRIO boot-up.

However, we found that the SRIO boot device configuration (section 2.5.2.2. of datasheet) shows that the device can only support either 4 unit of 1x lane or 2 unit of 2x lane.

Also, we would like to provide the 100MHz reference clock to the SRIO module but found SRIO boot device configuration does not provide such setting.

(Our FPGA cannot re-configure its SRIO module again to support 1x and 4x SRIO at the same time.)

Does that mean we cannot use SRIO boot-up in such case?

In order to provide a boot method to our DSP, we would like to use the I2C master boot to update the SRIO boot mode parameter table. Then, we can use the 100MHz reference clock to configure 4x lane of 3.125Gbps SRIO for download DSP firmware from FPGA.

But we are not sure whether it is work or not. Can you help to provide a detail description for this method? And what should be setting on the DSP hardware (I2C boot mode)?

In the reference schematic of C6678 EVM board, the DDR3 reference clock is 66.6667MHz. Can we use 100MHz as the reference clock for DDR3 PLL inside the DSP?

Any relationship required for this DDR3 reference clock and DSP core reference clock required? (such as same source, frequency within certain ppm, etc.)

AM5K2E04 complete datasheet

EASHWAR ARIVAZHAGAN — Thu, 23 May 2013 11:05:56 GMT

Sir/Madam

Can any one tell me when can we get the complete datasheet, technical reference manual and evaluation board for keystone multicore AM5K2E04 processor.

Please help....

Thanks in advance

executiion time of complex matrix multiplication

heung yong kang — Thu, 23 May 2013 05:02:47 GMT

hi,

i measured execution time of complex matrix multiplication using TSC.

C6678 run slower than i expect.

mesurement is right?

===== environment: EVM6678LE, CCS 5.2.1, C6000 complier 7.4, DSPLIB 3.1.0

===== codes:

#define LOOP_COUNT       10
#define CPU_FREQ             1e9               /* CPU freq = 1 GHz */
#define MSEC                        1e3               /* 1 sec = 1000 msec */

#define antenna_length (12)
#define sample_length (1024)

/* uca_output dimension = antenna_length x sample_length */
float uca_output[2 * antenna_length * sample_length];

/* uca_output dimension = sample_length x antenna_length */
float uca_output_trans[2 * antenna_length * sample_length];

/* uca_hermitian dimension = antenna_length x antenna_length */
float uca_hermitian[2 * antenna_length * antenna_length];

    TSCL = 0;
    t_start = TSCL;
    for (loop = 0; loop < LOOP_COUNT; loop++)
    {
        DSPF_sp_mat_mul_cplx(uca_output, antenna_length, sample_length, uca_output_trans, antenna_length, uca_hermitian);
    }
    t_stop = TSCL;

    printf("[complex multiply] loop = %d, row = %d, column = %d, execution time = %f msec\n", \
                LOOP_COUNT, antenna_length, sample_length, \
                1 / CPU_FREQ * (t_stop - t_start) / LOOP_COUNT * MSEC);

===== results:

[C66xx_0] [complex multiply] loop = 10, row = 12, column = 1024, execution time = 0.368105 msec

===================================================================================

SPI Programming error in C6678

Saurabh Anand — Wed, 22 May 2013 09:55:19 GMT

While building a simple program it is showing following error:

C:/ti/pdk_C6678_1_1_2_5/packages/ti/csl/cslr_device.h", line 45: fatal error #5: could not open source file "ti/csl/cslr.h"len

Please give me a solution to this problem

C6678 LVDS Clock input voltage

Xiaosong Kang — Wed, 22 May 2013 15:22:59 GMT

Hi, does C6678 core clock LVDS require 3.3V or 1.8V? In EVM, it looks like that it needs 3.3V. Also, Is there any recommendation of automotive grade (> 125 Deg. C) LVDS clock generator? Thanks.

how to use ddr3 x 2 ranks for 2048MB in C6678?

Youngju Lee — Tue, 21 May 2013 13:10:45 GMT

I am designing a schematic with C6678 and DDR3.

I want to have 2046MB(2GB) with 16M x 16 x 8 x 4 sdrams x 2 ranks with Micron MT41K128M16JT(16Meg x 16 x 8 banks).

C6678 EVM board(DSPM-8301E) have K4B2G1646C x 4 memory(total size :1GB).

But in this board, I don't know how to extend memory as like 2 ranks technology.

If anyone have any reference schematic or others, please share to me.

Best regards.

Young.

laserguy.young@gmail.com

Jtag problems of multiple c6678 devices

Zhongkai — Sun, 19 May 2013 16:41:15 GMT

In my design ,i use two C6678 chips . I want to debug the two dsps using 14 pin and 60 pin header separately. I have read the materials about the design for jtag emulation, but still have some questions.

(1) I am using the parallel trace configuration in my design, the user guide(spru655i Fig26) suggests that each processor have an independent termination resistor for emu signals, is it necessary? And for others signals , just as tck, tms and trst , do each processor need an independent termination resistor for them?

(2) The web http://processors.wiki.ti.com/index.php/XDS_Target_Connection_Guide#Multiple_Devices mentions that the design need series termination resistors for some signals, but the Fig 3-5 of spru589a don't mention that. Are the series termination resistors necessary? If used pull-up resistors, where should they placed, close to the emulator or to the dsp?

(3) I want to use one multiplexer/switch chip to select signals from 14 pin and 60 pin header. If I buffer the signals, where the buffer should be placed? Place one buffer after the multiplexer/switch chip or place two buffers before the multiplexer/switch chip.

PCIe impedance mismatch

David Meixner — Mon, 20 May 2013 19:34:23 GMT

The hardware design guide for C6657 requires a 100 ohm differential impedance for PCIe. However, I'm connecting to another device that requires 85 ohm. Any advice on how to resolve this?

Thanks,
David

how flow_id is defined and used and related with Rx channel in 10Gbe in K2?

weiqiang mao — Tue, 21 May 2013 07:50:19 GMT

Hi:

in 10Gbe@K2, Rx has total 16 channels, Is flow_id assignment related with Rx channel ID? what's the flow_id usage mechansim? how to config the flow_id for each Rx incoming packet? for 10Gbe, how many flows are supported?

thanks!

weiqiang