TI E2E Community
Digital Signal Processors (DSP)
C6000 Multicore DSP
Keystone Multicore Forum (C66, 66A, AM5)
Hyperlink boot address mappings?
The Bootloader user guide (spruggy5a) states:
HyperLink boot code initializes the chip-level interrupt controller to interrupt the DSPafter the boot. After setting up the interrupt configuration, the boot ROM executes anidle instruction. The remote device loads the memory directly and generates theHyperLink interrupt. When the boot code is awoken, the interrupt maps are restoredto their default values and the DSP branches to the address in DSP BOOT MAGICaddress. As with PCI, if the value in DSP BOOT MAGIC address is still 0 after wakeup,the ROM again executes an idle.HyperLink mapping can be configured by the master, but the bootloader sets up theinitial mappings.
But no information is given about what the actual HyperLink mapping setup is. Where can I find this info?
Anyone know where this information might be located?
We will add it in the next document version. The table is below.
Boot ROM Initialized HyperLink Segment Mapping
0 - N
Size of L2
Global address of Core0 L2 to CoreN L2
N + 1
N + 2
N + 3
Size of MSMC memory
N + 4
N + 5
N + 6
N + 7
N + 8
(N + 9) – 63
0x80000000 (4Mb steps)
N - Total number of cores. Check the data manual for the varying sizes.
If you need more help, please reply back. If this answers the question,
please click Verify Answer , below.
Excellent. Thanks Arun!
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