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Digital Signal Processors (DSP)
C6000 Multicore DSP
Keystone Multicore Forum (C66, 66A, AM5)
PKTDMA and Descriptors/LInked RAM
I had a general question on the performance when using descriptors and the associated entries in link ram. The link ram can handle 16000 entries only over 8 cores. I need probably of the order of double that i.e. 32K entries over 8 cores and so will have 16K entries in an external link ram stored in DDR3 together with all the 32K descriptors and the buffers that they point to all being stored in DDR3.
My question is what the is the performance tradeoff (i.e. how much loss in performance) in making use of the external link RAM in DDR3 over shared RAM over internal link RAM. Also what is the performance tradeoff with descriptors and buffers being stored in DDR3 as opposed to shared RAM or individual core RAM.
There is not much loss in performance when external linking RAM is used. However, I do not have figures supporting this. The external linking RAM is accessed by the QM_second master, whenever there is only pushing and popping of descriptors associated with the external linking RAM memory regions.
The descriptors and their associated buffers are operated on by the PktDMA peripherals (SRIO, NetCP, QM infrastructure etc). Hence, the performance here is determined by the data path from the PktDMA masters to the memory end points (CorePAC L2, MSMC or DDR3).
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Thanks for your reply. Can you quantify the order in the loss in performance (is it close to 1%, 10% etc) just due to using external linking RAM?
Can you also tell me the performance impact when the PKTDMA masters such as the NetCP is accessing memory end points (corePAC L2, MSMC vs DDR3)?
As mentioned in my previous post, I do not have quantitative figures for the performance loss, because of using external linking RAM instead of internal linking RAM. The throughput performance of peripherals mentioned in SPRABK5 (Throughput performance guide for C66x devices) discusses about the performance impact of PktDMA masters accessing different memory endpoints. Generally, for PktDMA peripherals like NetCP and SRIO, the throughput limiting factor is always the physical line rate (5 gbps per lane for SRIO) and not the throughput of the PktDMA master to memory end point (L2, MSMC or DDR3) data path.
However, for memory to memory transfers, using QMSS infrastructure PktDMA or EDMA3, the throughput of the PktDMA or EDMA3 TC master to different memory endpoints is important.
Can you point me to someone who may know or some document that may give me more info on the internal vs external linking RAM? I am not interested in the exact figure but I want to get a sense of the order of the loss in performance. Thanks for the SPRABK5 document link. Glad to know that the memory endpoint is not the limiting factor in PKTDMA peripherals like the NETCP and SRIO. Yes, I realize that EDMA3 master to different memory endpoints is impacted by the choice of memory endpoints but thanks for the heads up on the QMSS infrastructure PKTDMA impact as I intend to use that for core to core transfers probably from external DDR to external DDR3. I will have to study the impact in greater detail to see if that will suffice.
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