I have tried to go through the I2C boot process according to the recommended steps. But when I intend to return to the emulation boot mode by switch SW3[2:4] = '000', it failed and GEL output the bootmode=5 which is still in I2C bootmode.
Then I test some other switch status such as SW3[2:4] = '111' , but the GEL also read out the bootmode = 5.
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please make sure you apply a POR (Power on reset). The device configuration pins arelatched only during power-on reset.
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Do you mean POR as cut off the power and then power on the EVM?
I always do like that, but the situation remains.
yes that's want I meant. Or pushing the Full reset button on the EVM which also generates a POR.
Which EVM are you using? Are you using the on-board emulator?
Have you also tried re-launching CCS?
Yes, I have tried these method you mentioned.
And I'm using XDS560v2 on-board emulator and C6678EVMLE.
What's the possibility of the DIP switch become invalid and does not work?
could you check the content of the DEVSTAT register at address 0x02620020 using the memory window? (see 3.3.1 Device Status (DEVSTAT) Register in the datasheet)
Just to make check that the GEL file gives you the correct result ..
Checking the DIP Switch would be the next thing. I guess verifying the voltage levels at the DIP switch is quite easy on the EVM ...
Yes, I have checked the memory content of 0x2620020, it shows the bootmode value is 0x5, so the GEL gives the corresponding result.
The problem seems the new DIP switch value is not latched into the chip. I will check the voltage level later.
I have found the reason, I forgot to load the ibl to 0x80000000 before writing it to EEPROM, so the 0x80000000 hold the old value of the step of nand writing. After loading correctly , the BOOTMODE value become normal.
So why the wrong writing of EEPROM will take influence on the behavior of BOOTMODE? I checked the schematic of EVM, it seems the latched value of bootmode will be send to the FPGA XC3S200AN, so does it means it's the FPGA's responsibility to read the value of SW3[2:4] and latch it on the DEVSTAT register? Because FPGA's behavior is related to EEPROM's content, so the mistake take place in this process while wrong data located in EEPROM.
Am I right?Thanks.
yes that's correct. The FPGA sits in the middle between the DIP switches and the DSP. So if the FPGA is not programmed correctly this can lead to unexpected behaviour,
Thanks for sharing your findings with us ...
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