• Join
  • Sign In with my.TI Login
Texas Instruments
  • Products
  • Applications
  • Tools & Software
  • Support & Community
  • Sample & Buy
  • About TI
Sample & Purchase Cart Sample & Purchase Cart
  • Search
  • Advanced
TI E2E™ Community
  • Support Forums
  • Blogs
  • Groups
  • Videos
  • 简体中文
  • More ...
TI Home » TI E2E Community » Support Forums » Digital Signal Processors (DSP) » C6000 Multicore DSP » Keystone Multicore Forum (C66, 66A, AM5) » ISR
Share
C6000 Multicore DSP
  • Forums
  • Announcements
Options
  • Subscribe via RSS
Training Available
TI provides self-paced online training that introduces the primary components of the KeyStone II family of SoC devices.

  • KeyStone II SoC Overview >
  • KeyStone II Software Overview >
  • KeyStone II ARM Cortex-A15 Corepac Overview >
  • More Information >
  • Check out
    Multicore Mix blog
    • $core_v2_blog.Current.Name

      It’s our second anniversary, but you get the present!

      Posted 6 days ago
      by Lindsey Bare
      It’s hard to believe it’s already been two years...
    • $core_v2_blog.Current.Name

      Limited time offer: Save $100 on Keystone-based EVM!

      Posted 19 days ago
      by tscheck
      Have you been thinking about ordering a TI Keystone-based EVM...
    • $core_v2_blog.Current.Name

      Imagine the impact…TI’s KeyStone SoC + HP Moonshot

      Posted 30 days ago
      by Sanjay35057
      Last week, market leader Hewlett Packard announced a huge change...

    ISR

    ISR

    This question is answered
    RAHUL SHARMA91013
    Posted by RAHUL SHARMA91013
    on May 01 2012 05:24 AM
    Prodigy235 points

    Hi 

    I have a very basic question .

    I am working on C6670.

    Can i invoke another interrupt in an ISR itself ?

    for example 

    ISR()

    {

    some_queue_push_operation_foo( ) ;  // this push invokes another ISR

    }

    This is some kind of recursive interrupt.

    With Regards

    Rahul Sharma

    6670 intc
    Report Abuse
    • Reply
    You have posted to a forum that requires a moderator to approve posts before they are publicly available.
    All Replies
    • Chad Courtney
      Posted by Chad Courtney
      on May 01 2012 08:25 AM
      Mastermind22515 points

      When in an ISR, the GIE (Global Interrupt Enable) is off.  You can set the event, but the interrupt will not be taken until you exit the current ISR (i.e. they won't be nested.)

      Best Regards,
      Chad

      ------------------------------------------------------------------------------------------------------------

      Please click the Verify Answer button on this post if it answers your question.

      Report Abuse
      • Reply
      You have posted to a forum that requires a moderator to approve posts before they are publicly available.
    • Alberto Chessa
      Posted by Alberto Chessa
      on May 02 2012 04:35 AM
      Verified Answer
      Verified by RAHUL SHARMA91013
      Genius3740 points

      As already saied, the interrputs are normally disabled in an ISR, so the new interrupts will be served as soon as you return from the previous. Anyway You can reenable interrupts in your ISR so to nest them, but the underlaying Operative System (SYS/BIOS?) must support nested interrupts.

      Report Abuse
      • Reply
      You have posted to a forum that requires a moderator to approve posts before they are publicly available.
    • Chad Courtney
      Posted by Chad Courtney
      on May 02 2012 08:24 AM
      Verified Answer
      Verified by RAHUL SHARMA91013
      Mastermind22515 points

      Yes, as Alberto mentioned if using an OS, that has something along the lines of a SW Interrupt, where it's handled by SW and not true HW interrupts it's possible to do this. The term ISR is normally reserved for the usage with a HW interrupt, in which case it is required to disable the interrupts during processing because we're using physically registers such as the IRP to keep track of where to return for example so that we can put everything back the way it was when it's done processing.  With limited HW resources that means we cannot take any interrupts while processing another (the exception being an NMI or Reset which overrule GIE setting and are always processed.)  That said as Albert pointed out, SW interrupts could be implemented which do not use this HW but instead store the information in memory it has reserved and it can support nesting of these SW Interrupts, but they should not be referred to as ISRs.

      Best Regards,
      Chad

      ------------------------------------------------------------------------------------------------------------

      Please click the Verify Answer button on this post if it answers your question.

      Report Abuse
      • Reply
      You have posted to a forum that requires a moderator to approve posts before they are publicly available.
    TI E2E™ Community
    • Support Forums
    • Blogs
    • Videos
    • Groups
    • Site Support & Feedback
    • Settings
    TI E2E™ Community Groups
    • TI University Program
    • Make the Switch
    • Microcontroller Projects
    • Motor Drive & Control
    Other Communities
    • Deyisupport
    • Designsomething.org
    • beagleboard.org
    • TI on Element 14
    • TI on TechXchangeSM
    Other Technical & Support Resources
    • WEBENCH® Design Center
    • Product Information Centers
    • Technical Documents
    • TI Design Network
    • TI Technical Articles
    • TI Training

    All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.

    Content on this site may contain or be subject to specific guidelines or limitations on use. All postings and use of the content on this site are subject to the Terms of Use of the site; third parties using this content agree to abide by any limitations or guidelines and to comply with the Terms of Use of this site. TI, its suppliers and providers of content reserve the right to make corrections, deletions, modifications, enhancements, improvements and other changes to the content and materials, its products, programs and services at any time or to move or discontinue any content, products, programs, or services without notice.

    Follow Us Texas Instruments on Facebook Texas Instruments on Twitter Texas Instruments on LinkedIn Texas Instruments on Google+
    TI Worldwide | Contact Us | my.TI Login | Site Map | Corporate Citizenship | mobile m.ti.com (Mobile Version)

    TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs and
    embedded processors, along with software, tools and the industry’s largest sales/support staff.

    © Copyright 1995-2013 Texas Instruments Incorporated. All rights reserved.
    Trademarks | Privacy Policy | Terms of Use