Hi,
I am having an issue reading specific parts of core0 L2 SRAM via my PCIe driver. I have a little usermode device memory reading application which works as follows:
vpu_read <dsp addr> <length>
which calls the driver to read <length> bytes starting at <dsp_addr>. The utility outputs the bytes read to stdout. My driver determines what area of the DSP memory is to be read, and 'reconfigures' the IB address translation of PCIe BAR1 to target that area. Everything works fine, except when accessing particular addresses of core0's L2 SRAM. Other Core's L2 SRAM can be accessed fine. for example:
vpu_read 0x11804330 4 > out
vpu_read 0x21804330 4 > out
vpu_read 0x31804330 4 > out
...
All these work correctly, however, the following:
vpu_read 0x10804330 4 > out
gives me:
Precise External Abort on non-linefetch (0x1028) at 0xcf800030
(0xcf800000 is the kernel virtual address for the start of BAR1, bar 1 has been mapped to 0x10804300 here).
After this occurs, I look at 0x01846004 via JTAG (which is L2EDSTAT) and see that the bit corresponding to "Parity error occurred during DMA access" has been set.
I know this seems like a long shot, but this has me stumped. Any ideas?
Thanks,
Joel
