Hi,
I want to connect a NAND Flash with the C66x DSP, and it may be use the 8-bit ECC.
I want to know if you have the code of 8-bit ECC.
I find in the web of http://processors.wiki.ti.com/index.php/Raw_NAND_ECC#What_is_required_to_support_4b.2F8b_ECC_NAND_devices.3F. I find the OMAP device support 8-bit ECC in software.
Thank you,
Tianxing
C66x devices only support 1-bit and 4-bit hardware ECC detection. Note that using NAND that requires 8-bit ECC with 4-bit hardware ECC could have negative consequences, including boot failure.
If you must use 8-bit ECC enabled NAND, you need to use a software ECC algorithm like Reed-Solomon Code or BCH code (more efficient than RS code). These are very well documented algorithms and you should be able to find the code very easily on the Web.
In any case, here is a good app note from Micron that talks about hardware and s/w ECC solutions: http://www.micron.com/~/media/Documents/Products/Software%20Article/SWNL_implementing_ecc.pdf
Apparently they also provide software ECC drivers for their NAND products: http://www.micron.com/~/media/Documents/Products/Technical%20Note/NAND%20Flash/tn2962_large_page_NAND_drivers.pdf
This should be a good start. Let me know if you have any questions.
Regards,
Aditya
Hi Aditya,
Thank you for your reply, it is useful for us.
I can't find the source code of 8-bit ECC algorithm on the web, could you give me some advices.
Tianxing,
I am trying to find something for you that we might have developed internally.
At this time, we only have an internal test for 1-bit s/w ECC but that defeats the purpose since we already support 1-bit and 4-bit hardware ECC. I can try to find something useful for you online. In the meantime if you do come across something, please post it on this thread so that it will help the forum as a whole.
Thank you for your work to find the ECC algorithm for us.
Now, I found a 8-bit (or more bit) ECC algorithm on the web http://comments.gmane.org/gmane.linux.drivers.mtd/33552
It is a batch of Linux for the 1-bit software BCH ECC algorithm, and now it support 1-bit, 4-bit, 8-bit and more. And the author of code provide a benchmark in his PC as follow:
Test CPU: Intel(R) Core(TM) i5 CPU 650 @ 3.20GHz AECT = Average software encoding + correction time WECT = Worst software encoding + correction time AT = Average data throughput page size = 512 bytes BCH: 4-bit correction, using BCH_CONST_PARAMS=y, BCH_CONST_M=13, BCH_CONST_T=4 Errors AECT (µs) WECT (µs) AT (Mbit/s) ------------------------------------------- 0 0.690042 0.831818 5935 1 0.998295 1.08354 4102 2 1.05392 1.15312 3886 3 1.58135 1.68057 2590 4 1.64079 1.76482 2496 BCH: 8-bit correction, using BCH_CONST_PARAMS=y, BCH_CONST_M=13, BCH_CONST_T=8 Errors AECT (µs) WECT (µs) AT (Mbit/s) ------------------------------------------- 0 1.77351 1.82228 2309 1 2.76681 3.05114 1480 2 2.88904 3.40575 1417 3 3.39914 3.68515 1205 4 3.60047 4.26807 1137 5 5.27063 7.72297 777 6 6.36246 10.5239 643 7 7.74478 12.136 528 8 9.33835 16.4703 438
Now, I am finishing the code, if you have some advices for it, please tell me.
Thanks for posting this information. We will definitely look into leveraging this internally as well. I do not want to ask you to go out of your way here, but could you please post similar benchmark results if possible when you have implemented it on the DSP?
I will post benchmark results when I implemented it on the DSP that would be some weeks later.
I tested the performance of writing the NAND Flash on the board TMS320C6678EVM, however I found the speed is slowly at 800kB/s, the page write will consume 600 us. The datasheet provide the type value is 200us.
The datasheet of chip as follow:
5327.NAND512R3A2DZA6.rar
Did you have tested that? Would you give me some advices about that.
Hi Tianxing
Did you modified the IBL code and nand writer routines to support your nand flash ?
I have used in my design Nand flash (MT29F1G08ABBDAHC-IT) in x16 EMIF mode with 6678.
Can you please help me in which files of IBL i need to modify to support my nand flash.. ?
Thanks
Hi Mahendra,
I am sorry I can't help you.
I did't modify the IBL code, I only try to execute the ECC algorithm.
Hi Tianxing,
Thanks for your reply.
We have used 128MB Micron Nand flash connected to EMIF of C6678.
I gone through the MCSDK and now understood that I surely need to modify the NAND WRITER Utility to suite my nand.
My Doubt is Whether, the default IBL will support NAND READ for my 128MB nand flash ? ( Because If IBL supports nand read for all nand flash then I need not want to modify IBL for booting purpose, just modify nand writer , write to my nand and start booting)
Please suggest