I've tested the PCIe-Boot with a C6678-EVM and a PCIe-Adaptor-Card. Everything works fine, but debugging the cores and addresses it is obvious that only core 0 is running and the other cores are not started.
Core0 is in the while-Loop at the end of the program. The start address has written to 0x1x87FFFC for every core. The IPCGRx are written (I have modified the write with a Src, this can be seen with the debugger). But trying to loading symbols for Core1-7 failes, although the boot_magic_address 0xBABEFACE is not written.
How can I debug further to see whats going wrong on the other cores?
Moreover the output with minicom hung up everytime after some lines. I think that's no problem as Core0 runs until the loop is reached, but I wonder what's the problem (maybe UART-configuration of DSP or minicom)?
Thanks for help.Regards,Bernd
Did you load code to Core1-7 before writing the BOOT_MAGIC_ADDRESS? What are you using to write the BOOT_MAGIC_ADDRESS (BMA) of Core1-7, this should be done by Core0. Core0 should have it's BOOT_MAGIC_ADDRESS written first by PCIe, and then it should write the other Core's BMA.
You say you're trying to load symbols for Core1-7, I assume you're using CCS for debug then. Have you check that you got code loaded into the other Cores? What do you see in the BOOT_MAGIC_ADDRESS of Core1-7?
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I think I have understood some parts of the example wrong. The original example first initializes the DDR and then loads the bootCode into DDR. Core0 is then triggered via PCIe (by writing the Boot_Magic_Address). Then Core0 is booting and triggers Core1-7 (by writing the Boot_Magic_Address and sending IPC-IRQ).
Question for me is now: is it necessary to load the bootCode into the Local SRAM for every core? I don't think so as the code is present in the DDR. But I have modified the example so that the code is loaded into Local SRAM of Core0 (address 0x83CC40).
I think this is the problem as the other cores are not able to get bootCode from the Local SRAM of Core0 isn't it? So I'll try it with writing the bootCode to the MSM. I hope it is not necessary to load the code explicit to the cores if it is in a location where every code can get it?Regards,Bernd
Small update: Loading the bootCode to the MSM, then everything works!
You can run it out DDR3 as well. It's just a matter of what you use as your BOOT_MAGIC_ADDRESS.
I believe in theory you could run it out of another cores Local L2 space (using the global address - and everything linked as global addresses - you can't use local address as you'd be pointing to your core's Local L2 and not core0's L2) but it's not something I'd suggest doing.
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