Hello!Our board is similar to EVM6678L, except the vitex5 FPGA, clock settings and something else. We modified IBL code, and successfully ran sv01.out & sv04.out on our board. In the future, we want to use this application framework to satisfy our needs. My questions is :
1. Data frame of the input(RGB/YUV image at least @100fps) comes from SRIO, which is currently 1x, 2.5Gbps, DirectIO mode. How to change the RTP packets input to SRIO input?
2. We will add new algorithms in the system. As we understand, the algorithms must be xDM 0.9/1.0 compatible. MCSDK VIDEO 2.1 CODEC TEST FW User Guide has shown how to add a new codec in sv04, then we would like to know what about sv01.
3. We studied the 3 pkt-** demos and found the program flow is controlled by messages (siuVigdkIblDemo1080pTranscoding.c, siuVigdkIblDemo720to1080p.c, siuVigdkIblDemo720p.c). Then how can we generate the messages for our system application?
4. We highly appreciate the way of starting, configuration, communication, processing and so on in sv01. But it is a huge and complex project and it’s difficult for us to completely understand it and modify it. What’s the function of SIU, VPPU, MCCU, RCU, NDU, NEU, VTK, NWAL? How to add our code? Could TI provide more documents about sv01?Expect for your reply. Thanks very much!
Can you please provide more details about the application you are intending to build upon MCSDK Video?
1) Is it a multi-channel application or single channel? How will the eight cores be partitioned?
2) You mentioned input from SRIO. How about the output? Output via SRIO or Ethereal packets, or something else?
3) Can you please provide some description on the "new algorithms" to be added in your system? Are they video codecs or something else?
4) Can you please provide an overview of your system, such as the architecture and the data flow?
As you have experienced, there are two builds in MCSDK Video: sv01 and sv04. sv04 supports data IO via both TFTP and PCIe, while sv01 supports data IO via RTP. We can discuss which one is the better candidate for your system according to your application requirements.
In reply to Hongmei Gou:
1) Is it a multi-channel application or single channel? How will the eight cores be partitioned?>>>It is a single channel application. The eight cores will be partitioned to achieve better performance and real-time requirement .
2) You mentioned input from SRIO. How about the output? Output via SRIO or Ethereal packets, or something else?>>> Our board will play an important role in image processing and algorithms test. And it will be used multiple times in different subsystems. The picture bellow shows the case of CCD Camera. (1)Output is via ethereal packets in algorithms test; (2)Output is via SRIO in image processing of the real system.
3) Can you please provide some description on the "new algorithms" to be added in your system? Are they video codecs or something else?>>> They are image codecs. FPGA will do image preprocessing and DSP will do critical image processing, such as image enhancement, target tracking. We haven’t decided the details completely. The blocks of image enhancement algorithm are as follow.
4) Can you please provide an overview of your system, such as the architecture and the data flow?>>>As the pictures show, multicore DSP receives image data from SRIO and processes it real-time. The processed results transmitted to other subsystems via SRIO and optical fiber. The entire processing system works under the supervision of master control center. Therefore, the data flow can be described simply: SRIO --> DSP --> Ethernet or SRIO --> DSP --> SRIO.
In reply to PEI ZHOU:
Thanks for all the details about your application.
According to the information you provided, we would suggest using sv04 as the starting point of your application. sv04 suits for single channel applications, and it supports data IO via TFTP or PCIe. If your testing output to PC must be in RTP, sv04 can also be modified to support that as described in another E2E query: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/187260.aspx?pi70912=1. For dataIO via SRIO, need to add SRIO driver so that input/output data can be sent via SRIO.
In sv04, it is easy to add video codecs as well as other algorithms, such as the image processing algorithms you are intending. With dataIO implemented, plugging in a new algorithm will be mainly: 1) creating the algorithm instance; 2) algorithm processing call to process the input and generate the output data.
To answer your queston earlier about the acronyms:
SIU: System Integration Unit
VPPU: Video Protocol Processing Unit
MMCU: Multimedia Container Unit
RCU: RTP Control Unit
NDU: Network Driver Unit
NEU: Network Encapsulation Unit
VTK: Video Tool Kit
NWAL: Network Abstraction Layer
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