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DDR3 Performance Limited to 1333MT/s Usage Note

Daisuke Maeda
Guru 19835 points

C6678 datasheet (SPRS691C) describes that DDR3-1600 is supported. However, Usage Note 14 in the Silicon Errata (SPRZ334E) describes that DDR3 Performance is currently limited to 1333MT/s.

Why is this limited?

Is there the plan that this is not limited?

Best regards,

Daisuke

 

  • 0
    TI__Mastermind 30825 points

    The intent was to support DDR3-1600, but do to some internal issues there are problems operating it above DDR3-1333 reliably, we made improvements on the PG2.0 design to fix the issue, and while it did improve it, there was still timing issues that we could not fully meet DDR3-1600 requirements.  If/when we do another silicon revision of the device we well revisit this to see if further adjustments can be made, but for PG 1.0 and 2.0 of Si, their is the limitation to 1333 MT/s.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Guru 19835 points

    Hi Chad,

    Thank you for your reply.
    Sorry for my late reply.

    I hope that this limit is fixed in the next silicon revision.

    Best regards

    Daisuke

     

  • 0 in reply to Chad Courtney
    Expert 1630 points

    Hi Chad,

    Is there an update yet on this errata?

    Does the errata still apply to the faster 1.4GHz silicon speed variant ?

    Can the DDR3 be operated at some intermediate speed. e.g. DDR3-1500 ?

    Many thanks,

    Simon

  • 0 in reply to SimonPack
    TI__Mastermind 43660 points
    Hello Simon,

    The usage note 14 in the errata still applies to both silicon versions 1.0 and 2.0. Hope it will be fixed in the next version.

    Yes, this usage note applies to all the speed variants.

    As mentioned in the usage note, the DDR3 can be operated at any rate from 800MT/s to 1333MT/s only, beyond this range is not possible.

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Expert 1630 points
    Many thanks for your quick response.
    I was looking for an explanation for the errata. Is the limitation down to an internal race condition (rather than external signal integrity).
    If, as Chad states, PG2 is much improved over PG1, but still doesn't quite meet 1600, is it possible to meet something better than the PG1 limit.
    Is there a schedule for when PG3 will be released?
    Cheers,
    Simon
  • 0 in reply to SimonPack
    TI__Mastermind 46460 points

    Currently, there is no schedule to fix this limitation.  The current silicon implementation cannot operate above 1333MT/s and meet timing across all of the rated voltage and temperature ranges as well as the expected silicon process variations.

    Tom