Cache coherence in C6678

Youssef Lyoussfi

Hi,

I used the functions "CACHE_invL1d" and "CACHE_wbL1d" to provide cache coherence between L1d and MSMC.

In the document "DSP cache User guide" i found an example :

CACHE_InvL2(InBuffB, BUFSIZE, CACHE_WAIT);

The second argument is the "byte count", so i must specified it in Bytes, or i specified the buffer size without concideration of data type ?

Sincerly

Youssef

over 11 years ago

0 HRi over 11 years ago

Guru 10750 points

Hi Youssef,

The BUFSIZE is in bytes (a multiple of the cache line size) please check pdk_C6678_1_1_2_6\packages\ti\csl\csl_cacheAux.h

Thanks,

0 Brandy Jabkiewicz over 11 years ago in reply to HRi

Mastermind 6325 points

Hi Youssef,

I just did a lot of post about cache and learned some important points I will share.

1. The variables that you are invalidating should also be aligned on the cache line. It seems like if not the cache may not get invalidated the way you think.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/233503/824058.aspx#824058

2. Second, there is a silicon errata (I think they call it advisory 6) regarding the cache invalidate in a loop check setting. Here is my post about it:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/253690/894765.aspx#894765

Hope this is helpful for you to not waste lots of time debugging these issues.

Brandy

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Cache coherence in C6678