c6678 8 cores using cache has problem simultaneously

They have to write back one by one.  Otherwise they will overwrite each as you say.  In addition, you should keep in mind that if they are operating on the same cache line, then they will also corrupt each other with stale data in their cache.

Therefore, you need a semaphore around the cache write back, you need your data cache aligned and you also need to keep in mind the cache errata about the prefetch buffer.  (http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/253690.aspx)

BrandyJ,

Thanks for your relpy. My project maybe have a little difference with your post. In my projecy, core1~core7 's data is stored in 7 different areas in DDR, the 7areas all have

cache line aligned , and after core1~core7 process  different area 's  data ,they writeback, so they will not overwrite each. And I disable prefetch buffer.

I want to know  whether I need to  write back one by one in my case.

Best Regards,

Si

Oh - with more details, it sounds like your project would be ok.  As long as each core has their own cache aligned memory space like you said I think it would work. 

But actually,it doesn't work well if I don't do writeback one by one, else it work well. So I have no ideas why it is.

Chad,

yeah,after core1~core7 process their data, they all use global cache operation to writeback and Invalidate .here I have two probelm:

1. you said " there's no known issues with performing WB's simultaneously from all cores caches at the same time". So I want to know why my project don't work well if don't

do writeback one by one

2.you said  "you probably want to do a Writeback and Invalidate if you're expecting one core to read all of the data that was written back by all of the cores, otherwise it will still grab whatever is in it's cache as it's still marked valid". My project core0 will collect core1~core7 ’s data, and for core0, it just to do a Invalidate ,and for core1~core7 they just need to do a Writeback  to write the data in cache back to DDR, and next time core1~core7 start to process, they need to do a Invalidate. Is my idea uncorrect？

 Best Regards,

Si

Si,

1.) I suspect the behavior is as expect on the Si side, but your code is missing a step and thus the results are not what you expect them to be as a result.

2.) Since core0 is doing the checking, it will need to Invalidate everything that it's checking on Core1-7 prior to each check.  

Best Regards,

Chad

Chad,

1 you said "but your code is missing a step ", I am not clear what step my code is missing. core1~core7's use one image that is put in MSM RAM, and every core's section

in cmd except text section in MSM RAM,all in LL2. They just process  the data that core0 give on DDR ,and after put back to DDR.

2 yeah, core0 need to do a Invalidate ,but for core1~core7, they just  need to do a writeback after process,is it right?

Best Regards,

Si

1.)  I said that I suspect that is the case.  I don't know everything that your code is doing, so we're working through these details to figure out what is being missed :-)  The more details about the total data movement on each of the cores and modifications and steps that are being done the better understanding I'll have to see if WB's are sufficient or WB/Inv is required.   To be honest if you want a cover everything solution, perform a Wb/Inv on everything after processing is done on data (and before some other core attempts to access that data - and perform an Invalidate of cache before accesses data from DDR that others have modified.)

2.) That's correct.  This assumes coreA where A  != 0 data is not modified by coreB were B != A inbetween accesses (i.e. Core0 isn't modifying it in between either.)  If Core0 or some other core is modifying coreA's data in between the processing, then coreA should also be performing WB and Invalidate.

Best Regards,

Chad