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Twin die DDR3 supported in C6678?

g.f.
Guru 15510 points

Hi,

I have a question about C6678 DDR3.

Does C6678 support twin die DDR3?
We are planning to use micron MT41K512M16(32 Meg x 16 x 8 Banks).
This memory is DDR3L and have twin die.

This is low voltage DDR3, so we will provide 1.5V for DDR3 I/O.

best regards,
g.f.

  • 0
    TI__Mastermind 46460 points

    g.f.

    We do not ket have a configuration sequence for twin-die DDR3 implementations on the C6678.  Is this an existing board design or one that is in the design stage?

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Guru 15510 points

    Hi Tom,

    Thank you for the reply.

    Actually this question was from my customer.
    They are considering a device right now, so that it's not in design stage yet.

    I saw the following post which you replied:
    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/280884/980452.aspx#980452

    In that post, you said that twin-die devices are fully supported.
    Do you mean it wasn't supported yet?
    So, C6678 only support single die DDR3 for now, right?
    By the way, does it support in the future?

    They need 4GByte DDR3 for their system, but there are board space limitation.
    The largest DDR3 in the market is 8Gbit from micron which is twin die,
    so that they was thinking to use 8Gbit(twin Die) x 4 DDRL3 memory.

    best regards,
    g.f.

  • 0 in reply to g.f.
    TI__Mastermind 46460 points

    g.f.

    As you saw in that other post, the debugging was never concluded.  There were layout issues that complicated the analysis.  I requested an update on this design debug.

    The C6678 does support 2 ranks of DDR3 memory.  However it does not support mirrored addresses on the 2nd rank.  This prevented testing of the second rank during device qualification since all dual-rank UDIMMs available at that time required address mirroring.

    Twin-die devices are only recently becoming cost competitive.  We do not know of any reason they should not work with the C6678 but we do not have a board with that configuration.  We are planning some tests over the next few weeks using twin-die devices.

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Guru 15510 points

    Hi Tom,

    Thank you for the reply.

    Let me ask again to make me sure.

    My customer need 4GByte DDR3 for their system but they are't thinking of using dual rank(UDIMM).
    The available DDR3 solution is single die for C6678 now,
    so that customer should select DDR3 which is listed in
    "DDR3 Design Requirements for KeyStone Devices(sprabi1a)" page.11
    Table 1 and Table 2, right?

    If you get the result of twin-die test, please let me know.

    best regards,
    g.f.

  • 0 in reply to g.f.
    TI__Mastermind 46460 points

    g.f.

    Yes, that table is the reference.  As stated previously in this thread, the configuration for the dual rank options is still being verified and not a proven solution today.

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Guru 15510 points

    Hi Tom,

    Thank you so much for the reply.
    And I'm sorry for the delay.

    I understood and will tell my customer.

    best regards,
    g.f.

  • 0 in reply to Tom Johnson 16214
    Prodigy 130 points
    Hi Tom
    There are 4 combination for DDRSLRATE[1:0],(fastest,fast,low,lowest)
    i want to know How many differences in memory actually read and write speed with different parameters（fastest,fast,low,lowest），thanks！
  • 0 in reply to bing zhou
    TI__Guru* 81335 points

    Hi ,

    We strongly recommend you to create new e2e posts for your queries by referring the information from old forum posts if needed. The new threads gets more attention than old threads and please do not duplicate the queries on multiple threads.


    Thank you for your patience.

  • 0 in reply to g.f.
    TI__Mastermind 46460 points

    The KeyStone I DDR3 Initialization Application Report (SPRABL2D) was revised in January of 2015.  It now contains instructions for configuring the Controller and PHY to support twin-die SDRAMs.  This was not validated on any TI reference design but we provided this guidance as a service to customers eager to try it.  Based on feedback from those who implemented this, we believe that this configuration is valid.  However, we do not have confirmation that this was ever implemented on a board that went to production.  There were reports that some boards that implemented twin-die devices had layout issues resulting in occasional errors.  More recently monolithic 8Gb DDR3 SDRAM devices became affordable and we have not seen interest in twin-die use since then.  As stated previously, we believe that the guidance provided is sufficient for success but we cannot guarantee it since we did not characterize it on a TI reference platform.  Therefore, our current recommendation is to implement DDR3 SDRAM topologies using monolithic (single-die) SDRAMs.

    Tom