66AK2H MSMC MPAX register access

It looks to me from the diagram you're simply changing the address mapping configuration, correct?  As long as you follow the guidelines and restrictions as you've pointed out, this is perfectly valid.

I general this is done as a one time upfront change, if you're planning on changing it dynamically, you'll need to put SW in place to make sure that no system ports access the SES Interface frome the same PrivID, but it would be allowable.

Best Regards,

Chad

Chad-san,

Thank you for your prompt response.
Your understanding is almost correct, but I would like to compensate a little bit.

Chad Courtney said:

you'll need to put SW in place to make sure that no system ports access the SES Interface frome the same PrivID, but it would be allowable.

During changing segment 1, other SoC master(EDMA etc..) will always access segment 0 from the same PrivID. 
Is it allowable? (Note that no access on segment 1.)

Best regards, RY

Chad-san,

Thank you so much for your support.
To satisfy the MPAX configuration rule, I am considering other method.
May I confirm if the following situation is allowed or not?

I would like to change MPAX register dynamically.
From previous your answer, I understood:
  Modifying the MPAX registers during other SoC master access to the segment is NOT allowed.
Instead, I am considering to use sRIO (Direct I/O) to access both data segment and MPAX registers. (There is no other SoC master access.)

From the macro point of view, it means only one access to SES Interface at a moment.
It can be satisfy the MPAX configuration rule. Is that right?

For detail, I would like to send you pdf file.
It must treat as confidential. Do you have any method to send it to you?

Best regards, RY

As long as it's not violating the other requirements "It is required that updates to memory-mapped registers are not made while accesses are being made through any of the system ports that utilize the registers being written to." then it's valid.  The SRIO isn't violating this, but make sure there's no other traffic that would be violating it as you're changing the MPAX configuration.

Best Regards,

Chad

Chad-san,

I am sorry. I had misunderstanding about previous question.
May I have once more confirmation?

RY9983 said:

From the macro point of view, it means only one access to SES Interface at a moment.

It can be satisfy the MPAX configuration rule. Is that right?

From the macro point of view, there are two types of access.
  access a) sRIO to DDR3A via MSMC SES Interface.
  access b) sRIO to MPAX registers via MSMC SMS Interface.
But, sRIO issues only one transaction either access a) or b) at a moment.

It can be satisfy the MPAX configuration rule. Is that right?

Best regards, RY

Ry,

Assuming that the MPAX registers being modified in b.) are for the control of addressing used in a.) then this would be violating the requirements.

Best Regards,

Chad

Chad-san,
Thank you for your reply.

Chad Courtney said:

Assuming that the MPAX registers being modified in b.) are for the control of addressing used in a.) then this would be violating the requirements.

I understand.
May I have confirmation along my case.
In my considering case, there are two data streaming (streaming A and B).

I am considering like following:
streaming A :
  a. Data transfer from sRIO to DDR3(area A)
  b. After that, MPAX addressing is modified to area C from area A.

streaming B :
  c. Data transfer from sRIO to DDR3(area B)
  d. After that, MPAX addressing is modified to area D from area B.

During "a" of streaming A, "d" might be occured. (During "a" of streaming A, "b" has never been occured.)
Can It be satisfied the MPAX configuration rule?

And, I am asking to local FAE support to send you confidential pdf file.

Best regards, RY

Chad-san,

Thank you so much!
Your suggestions are very helpful for us.

In conclusion, there are two method you said:
  Method A) use NWRITE_R for the last DDR3 write transaction
  Method B) use NWRITE followed by a DOORBELLL packet

In our system, I would like to use sRIO as 5Gbps x2lane x2port mode.
Each ports are connected to FPGA, and both sRIO ports stream data to 66AK2H from FPGA.

Q1) In this case, can I use "Method B"?
Q2) When I use "Method A", can you imagine the actual throughput?

About Mehtod B, I am considering to following process.
  Step 1) SWRITE: Data streaming
  Step 2) DOORBELL: Wait for previous SWRITE transaction
  Step 3) NWRITE_R: Change MPAX register
  Step 4) SWRITE: Consecutive data streaming

Best regards, RY

Chad-san,

Thanks!!  Do you have consideration about Q2?

RY9983 said:

Q2) When I use "Method A", can you imagine the actual throughput?

Best regards, RY

RY,

I think that's really going to be system dependent.  If moving large amounts of data in between changes, then the impact should be minimal and approaching the throughput numbers documented in the Throughput Application note.

Best Regards,

Chad

Chad-san,

Thank you for your reply.
"the Throughput Application note" is sprabk5a. Right?
http://www.ti.com/lit/an/sprabk5a/sprabk5a.pdf

Do you have throughput document for KeystoneII?
Or, could you let me know its release schedule?

Best regards, RY

RY,

Yes, that's the Throughput App Note, I referred to.  There's not a separate one for Keystone II devices.  The SRIO Throughput performance numbers are going to be the same.

Best Regards,

Chad

Chad-san,

Thank you for your seamless support !

Chad Courtney said:

Yes, that's the Throughput App Note, I referred to. There's not a separate one for Keystone II devices. The SRIO Throughput performance numbers are going to be the same.

Although there is NWRITE performance in sprabk5a, NWRITE_R performance does not exist.
Do you have NWRITE_R performance ?

Best regards, RY

Hello,

I am evaluating the changing of MSMC segment by sRIO direct I/O transfer.
In our exam, I am using DualEVM_BOC board to connect both K2HEVM and 6678EVM.
And, sRIO transfer is succeeded from C6678 to DDR3A/sRIO cfg area.
But, when I perform NWRITE transfer to MSMC config registers area(0x0BC00000) by C6678, "RX IO Access" error is happened in K2H side ERR_DET(0x0290C008) register.
I am using PDK example:

 - K2HEVM side: 
    C:\ti\pdk_keystone2_3_00_04_18\packages\exampleProjects\SRIO_TputBenchmarkingK2KC66TestProject

 - C6678EVM side:
    C:\ti\pdk_C6678_1_1_2_6\packages\ti\drv\exampleProjects\SRIO_TputBenchmarkingTestProject

Question)
Do you have any idea to avoid this error?
Do I have to set sRIO as supervisor mode?

If you need more information, please let me know.

Best regards, RY

Hello,

Do you have any update?

First, I would like to know..
What is happened when RX IO Access error flag assert?

Best regards, RY

Travis-san,

Thank you for your reply.

- The sRIO direct-IO mode can access to MPAX registers. Is that right?

- To become the supervisor mode, I configured following register:
SUPRVSR_ID (0x02900E4C) = Transfer ID (0x2 in my case)
I could see the 0x2 in ID_CAPT (0x0290C018) register.
Do I have to configure other registers?

Best regards, RY