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Keystone II DDR3 Connection impications on DSP and ARM performance

What are the implications of having DDR3 memories on only the A bus or the B bus (one is tied directly to the TERANET, the other to the MSMC):

  • for ARM performance?
  • for DSP performance?

Charles

  • Charles,

    The DDR3B is intended for supporting things like Accelerators and some extra data traffic on the Cores.

    The key differences are going to be the following.

    DDR3B:

    No Coherency between a DSP CorePac and other CorePacs (ARM or DSP), EDMA, SoC Masters

    No Coherency between an ARM CorePac and other ARM CorePacs, EDMA, SoC Masters

    No Automatic coherency w/ XMC Prefetch buffer.

    Limited to 2GB of addressable space.

    Sharing DDR3A between the ARM and DSP cores, especially for program data is expected.  And also data which is shared (and needs to maintain coherency between masters/corepacs) would likely be placed in DDR3A space.

    For other items such as processing data by accelerators that would probably want to be off in DDR3B (assuming it's populated with memory.)

    Best Regards,
    Chad

  • hi, Chad:

        You said that DDR3B :No Coherency between a DSP CorePac and other CorePacs (ARM or DSP), EDMA, SoC Masters.

        I can't understand the words "No Coherency“ well, according to my point, No Coherency is that if two master handle with data, hardware will not maintain the data Coherency , so we should maintain the data Coherency by software.

        Is my understand correct?

        Best Regards

             Gavin

  • Gavin,

    Your understanding is correct. 

    Best Regards,

    Chad

  • hi, Chad:

       Thank you for your clarification,  I have further question to consult you.

        In the SPRS866E, page30, Table 4-1, It say that below:

    Cortex-A15 Processor Core Supported Features:

    Support for coherent memory accesses between A15 cores and other non-core master peripherals (Ex: EDMA)
    in the DDR3A and MSMC SRAM space.

    From my point of view, the meaning of this sentence is that if data in the DDR3A and MSMC SRAM space, two mastar deal with the data should not maintain coherence by software, hardware will maintain coherence automatically.

        Is my understanding correct?

        Best Regards

             Gavin