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SRIO inizialization error (C6678)

I'm trying to use the SRIO module, but the inizalization fails every time.
In the SPn_ERR_STAT register i see that the bit Port Uninitialized is always 0.

This is my code, copied from one of the example in the PDK

void CSRIO::Setup(UINT16 DeviceID16, UINT8 DeviceID8)
{
/* SRIO power domain is turned OFF by default. It needs to be turned on before doing any SRIO device register access. */

// 1. Power on SRIO
prPSC_PDCTL[4] = 1; //SRIO = Power Domain n.4

// 2. Enable the clocks too for SRIO
prPSC_MDCTL[11] = 3; //SRIO = Module Control Register n.11

// 3. Start the state transition
rPSC_PTCMD |= (1 << 4); //SRIO = Power Domain n.4

// 4. Wait until the state transition process is completed.
while (rPSC_PDTSTAT) ;


/* SRIO initialization sequence. */
// 5. Disable SRIO reset isolation
prPSC_MDCTL[11] &= ~(1<< 12); //SRIO = Module Control Register n.11

// 6. Disable the SRIO Global block
rSRIO_GBL_EN = 0; //Global Enable

// 7. Disable each of the individual SRIO blocks.
for(int k=0; k<=9; k++)
rSRIO_BLK_EN(k) = 0; //Block Enable (0-9)

// 8. Peripheral Initialization
rSRIO_PER_SET_CTL = (0 << 30) | (0 << 28) | //MAU & LSU Little Endian - Big Endian Swap
(0 << 27) | //Supports only packets where DestID equals BASE_ID or any of the device IDs or 8 multicast IDs.
(0 << 24) | //Set boot complete to be 0 - Write to read only registers enabled
(0 << 22) | //TXU & RXU Little Endian - Big Endian Swap
(0 << 21) | //Enable automatic promotion of response priority by RXU and MAU.
(1 << 18) | //Min 2 logical layer TX buffers needed to send priority 2 packets
(2 << 15) | //Min 3 logical layer TX buffers needed to send priority 1 packets
(3 << 12) | //Min 4 logical layer TX buffers needed to send priority 0 packets
(0 << 9) | //VBUS transaction highest priority
(5 << 7); //VBUS frequency prescaler of 416,66 MHz (SYSCLK10 = SYSCLK1 / 3)

rSRIO_PER_SET_CTL1 = (0 << 8) | //Class of Service disabled
(0 << 2) | //SYS_CLK is selected based on: TX0
(0 << 1) | //RXU will not block any context based on the priority
0; //On a response CRF is the same as the incoming request

// 9. Now enable the SRIO block and all the individual blocks also.
rSRIO_GBL_EN = 1; //Global Enable
for(int k=0; k<=9; k++)
rSRIO_BLK_EN(k) = 1; //Block Enable (0-9)

// 10. Unlock the Boot Configuration Kicker
KICKUNLOCK()

// 11. Setup the PLL
//Reference Clock = 156.25 MHz
rSRIO_SERDES_CFGPLL = (0 << 13) | //No Clock Bypass
(0 << 11) | //Frequency Dependent Bandwidth
(0 << 9) | //VRange = High frequency
(0x40 << 1) | //Using 156.25 MHz RefClk ---> MPY = 0x28 for 3.125 Gbps or MPY = 0x40 for 5 or 2.5 or 1.25 Gbps
1; //Enable

// 12. Wait for stable PLL
while (!( rSRIO_SERDES_STS & 1)) ;

// 13. Setup the Receiver and the Transmitter
for(int k=0;k<4;k++)
rSRIO_SERDES_CFGRX(k) = (1 << 22) | //Offset compensation enabled
(1 << 18) | //Fully adaptive equalization
(6 << 15) | //Clock/data recovery: 110b = First order with fast lock
(0 << 12) | //Loss of signal disabled
(0 << 10) | //Comma Alignment disbled
(1 << 7) | //Termination programmed to be 001 (FIXED)
(0 << 6) | //Normal polarity
(1 << 4) | //Half rate. Two data samples per PLL output clock cycle
//MPY = 0x40 , RATE = 1 ---> 5 Gbps
//MPY = 0x28 , RATE = 1 ---> 3.125 Gbps
//MPY = 0x40 , RATE = 2 ---> 2.5 Gbps
//MPY = 0x40 , RATE = 3 ---> 1.25 Gbps
(2 << 1) | //Bus Width 010b (20 bit) (FIXED)
1; //Enable

for(int k=0;k<4;k++)
rSRIO_SERDES_CFGTX(k) = (0 << 20) | //Synch master
(0 << 19) | //Transmitter pre and post cursor FIR filter update
(0 << 14) | //Adjacent post cursor Tap weight 0%
(0 << 11) | //Precursor Tap weight 0%
(0xF <<7) | //Swing max.
(0 << 6) | //Normal polarity
(1 << 4) | //Half rate. Two data samples per PLL output clock cycle
//MPY = 0x40 , RATE = 1 ---> 5 Gbps
//MPY = 0x28 , RATE = 1 ---> 3.125 Gbps
//MPY = 0x40 , RATE = 2 ---> 2.5 Gbps
//MPY = 0x40 , RATE = 3 ---> 1.25 Gbps
(2 << 1) | //Bus Width 010b (20 bit) (FIXED)
1; //Enable

rSRIO_SERDES_CFGTX(0) |= (1 << 20); //Synch master (When aggregating multiple lanes, lowest numbered channel in the aggregate must have MSYNC = 1.)

// 14. Clear the LSU pending interrupts. */
rSRIO_LSU0_ICCR = 0xFFFFFFFF;
rSRIO_LSU1_ICCR = 0xFFFFFFFF;

// 15. Set the 16 bit and 8 bit identifier for the SRIO Device. */
rSRIO_BASE_ID = (DeviceID8 << 16) | DeviceID16;

// 16. Set the Host Device Identifier.
rSRIO_BID_LOCK = DeviceID16;

// 17. Enable TLM Base Routing Information for Maintainance Requests & ensure that the BRR's can be used by all the ports. */
// 18. Configure the Base Routing Register to ensure that all packets matching the Device Identifier & the Secondary Device Id are admitted. */
for(int i=0; i<4; i++)
for(int j=0; j<4; j++)
{
/*TLM port 0 base routing register 0 Control not supported by TI*/
if (i == 0 && j == 0) j++;

pSiSRIO_PORT_TLM[i].brr[j].ctl = (1 << 31) | //Enables the BRR for use in accepting and routing inbound packets.
(1 << 26) | //Maintenance request/reserved packets with destIDs matching this BRR routed to the LLM
(0 << 24); //Configures the BRR to be used only by all ports in the path.

pSiSRIO_PORT_TLM[i].brr[j].pattern_match = 0xF00DFFFF; //F00D 16b-id 
}

/* Configure the component tag CSR */
rSRIO_COMP_TAG = 0x0; //Useful for devices without device IDs.

/* Configure the PLM for all the ports. */
for (int n = 0; n < 4; n++)
{
/* Set the PLM Port Silence Timer. */
pSiSRIO_PORT_PLM[n].silence_tmr = 0x50000000; // Silence Interval is SRV_CLK period X 410 X SILENCE_TIMER.

/* Enable Input & Output Port */
pSiSRIO_PORT_CSR[n].ctl = 0x00600001;

/* Set the PLM Port Discovery Timer. */
pSiSRIO_PORT_PLM[n].discovery_tmr = 0x50000000; //28 msec

/* Reset the Port Write Reception capture. */
pSRIO_PW_RX_CAPT[n] = 0;
}

/* Set the Port link timeout CSR */
rSRIO_SP_LT_CTL = 0xFFFF << 8; //Port Link Timeout = 629,14us - Longest: SRV_CLK period * TIMEOUT_VALUE * 4 [SRV_CLK = 416,66 MHz (SYSCLK10 = SYSCLK1 / 3)]

/* Set the Port response timeout CSR */
rSRIO_SP_RT_CTL = 0x1FFFFF << 8; //Port Response Timeout = 600ms - Timeout = 15 x((Prescale Value + 1) x DMA Clock Period x Timeout Value)

/* Set the Port General CSR: Only executing as Master Enable */
rSRIO_SP_GEN_CTL = 0x40000000; // agent, master, undiscovered

/* Clear the sticky register bits. */
rSRIO_REG_RST_CTL = 1;

/* Set the device id to be 0 for the Maintenance Port-Write operation to report errors to a system host. */
rSRIO_PW_TGT_ID = 0;

/* Set the Data Streaming MTU */
rSRIO_DS_LL_CTL = 0x40; //256B

/* Configure the path mode for the ports. */
for(int n=0; n<4; n++)
pSiSRIO_PORT_PLM[n].path_ctrl = 4; //4-Lane Mode

/* Set the LLM Port IP Prescalar. */
rSRIO_PRE_SRV_CLK = 0x00000019; // IP_CLK = TXBCLK = 1/20th the data rate (5GBaud) = 250MHz

/* Enable the peripheral. */
rSRIO_PCR = 0x00000005; // Assert the PEREN bit to enable logical layer data flow

/* Configuration has been completed. */

// Set BOOT_COMPLETE bit
rSRIO_PER_SET_CTL |= (1 << 24);

/* This code checks if the ports are operational or not. */
//INIT_WAIT - Wait for lane initialization
//Read register to check portx(1-4) OK bit (4 port) polling SRIO_MAC's port_ok bit
for(int i = 0; i < 4; i++)
while (!(pSiSRIO_PORT_CSR[i].err_stat & 0x2)) ;

/* Set all the queues 0 to operate at the same priority level and to send packets onto Port 0 */
for (int i =0 ; i < 16; i++)
prSRIO_TXQ_SCH_INFO[i/4] |= (((0 << 4) | (0)) << ((i & 3)*8)); //Port 0, CRF 0

/* Set the Doorbell route to determine which routing table is to be used
* This configuration implies that the Interrupt Routing Table is configured as follows:-
* Interrupt Destination 0 - INTDST 16
* Interrupt Destination 1 - INTDST 17
* Interrupt Destination 2 - INTDST 18
* Interrupt Destination 3 - INTDST 19
*/
rSRIO_INTERRUPT_CTL = 0; //RIO Doorbell Interrupts routing table is for the dedicated interrupts

/* Route the Doorbell interrupts.
* Doorbell Register 0 - All 16 Doorbits are routed to Interrupt Destination 0.
* Doorbell Register 1 - All 16 Doorbits are routed to Interrupt Destination 1.
* Doorbell Register 2 - All 16 Doorbits are routed to Interrupt Destination 2.
* Doorbell Register 3 - All 16 Doorbits are routed to Interrupt Destination 3. */
for (int i = 0; i < 4; i++)
{
for (int j = 0; j < 16; j++)
{
if (j < 8)
pSiSRIO_DOORBELL_ICRR[0].reg_1 |= (i << j*4);
else
pSiSRIO_DOORBELL_ICRR[0].reg_2 |= (i << j*4);
}
}

/*Clear Error Detect registers*/
rSRIO_ERR_DET = 0x00000000; //Error Detect register - All Clear
rSRIO_ERR_EN = 0x00000000; //Error Enable register - All Disabled

/*Clear Capture registers*/
rSRIO_H_ADDR_CAPT = 0x00000000; //High Address Capture - clear
rSRIO_ADDR_CAPT = 0x00000000; //Address Capture - clear

rSRIO_ID_CAPT = 0x00000000; //Device ID Capture - clear
rSRIO_CTRL_CAPT = 0x00000000; //Control Capture - clear

/* Initialization has been completed. */

}

Can anybody help? Thanks