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TMS320C6678 CorePac clock (SYSCLK1) minimum frequency

Other Parts Discussed in Thread: TMS320C6678

TMS320C6678 datasheet Table 2-24 shows a minimum CorePac frequency of 800MHz, regardless of the input clock frequency. In each case, the PLL divider and PLL multiplier settings are always changed to make the CorePac frequency 800MHz.

The C6678 Power Consumption spreadhseet shows the minimum CorePac clock frequency is 800MHz and won't let me enter any frequency lower than that. I want to reduce device power dissipation; if I can meet the processing - timing requirements running the CorePacs at 500MHz or 400MHz, I would like to do so.

Can the TMS320C6678 CorePac clock frequency be configured for less than 800MHz?

If no, why not?

Thank you for your time

  • Hi James,

    Full operation of all interfaces requires a minimum core clock frequency of 800MHz. The device is only tested down to that frequency and there are a number of internal clock domain transitions that may not operated at core clock speeds that are lower. We cannot support core clock speeds slower than 800MHz.

    Regards, Bill