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upp transmit (channel Q) problem

Jan Debiec
Prodigy 170 points

Hello,

based on post from Valada Belary (http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/202118.aspx),

I have build my project with UPP transmission in both directions.

Receive is working perfect , my RX , (Channel-I) configuration 86 lines of 256 bytes in one window, 

but I have issues with Q channel:

I have defined a window with one line, 64 Bytes, but DSP transfers 2 times the same contents of 64 Bytes, i.e. One window with 2 equal lines.

I have checked the contents of UPQD0,1,2 registers, it'S ok, but the line is 2 times sent.

Any idea?

Jan

  • 0
    TI__Mastermind 20790 points

    Jan,

    To program a DMA transfer, write the appropriate fields in the DMA channel descriptor registers, UPIDn for DMA Channel I or UPQDn for DMA Channel Q.

    The UPxS2.PEND bit reports whether a new set of DMA parameters may be written to the DMA descriptor registers. Each DMA channel can have at most one active transfer and one queued transfer.

    Go through the section "2.6.1 Step-by-Step Procedure" in the KeyStone Architecture Universal Parallel Port (uPP) User Guide.

    Transmit Mode: The FIFO is divided into blocks that can be set to 64, 128, or 256 bytes, configured by the TXSIZEA or TXSIZEB field in the uPP threshold configuration register (UPTCR).

    If possible please provide a code snippet so that we can examine this issue.
    In addition that, refer this E2E post, it may help you.
    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/270840/949136.aspx#949136

  • 0 in reply to Pubesh
    Prodigy 170 points

    Hi Pubesh,

    thank for your reply.

    As I said before, I have implemented my code based on TI-sample code.

    Receiving:

    I have configured one window, with 86 lines, with 256 Bytes in every line, with IRQs after every Line and Window:

    It's working perfect.

    Transmitting:

    One window with one line with 64 Bytes:

    Threshold = 64Bytes, 

    UPQD0 = pointer to myDate

    UPQD1 ; lineCnt = 1, BytesPerLine = 64

    UPQD2; lineIndex = 64

    The result:

    DSP transfers one window with _TWO_ lines with the same contents: 2 * 64 Bytes 

    Error: I get two times the same content, instead of one (measured with Altera Quartus SignalTab LogicAnalyzer)

    Best regards

    Jan

  • 0 in reply to Jan Debiec
    TI__Mastermind 20790 points

    Jan,

    Did you find the reason on this issue? If possible please provide a code snippet so that we can examine this issue. 

  • 0 in reply to Pubesh
    Prodigy 170 points

    Hello Pubesh,

    here is function which I call to start UPP TxTransfer with some defines:

    //Tx defines
    #define eTxLineCnt (1)
    #define eTxLineSizeInBytes (64)
    #define eTxXferSize (eTxLineCnt * eTxLineSizeInBytes)

    ...

    void prepareUppDmaTxTransfer(void)
    {
    char * uUppTxBuf;

    uUppTxBuf = (char*)g_sUppTxBuffer.au8TxBuffer + 0x10000000;

    // init DMA channels
    while(CSL_FEXT(uppRegs->UPQS2, UPP_UPQS2_ACT) == 0)
    upp_dma_prog(UPP_DMA_CHAN_Q, (void *)uUppTxBuf, eTxLineCnt, eTxXferSize / eTxLineCnt, eTxXferSize / eTxLineCnt);

    }

    In attachment is a screenshot from  Altera LogicTab, 

    i_sl_UPP_CHB_EN: signal seen from FPGA, Tx from DSP: ChannelQ_Enable,

    i_sl_UPP_CHB_START: signal seen from FPGA, Tx from DSP: ChannelQ_START,

    is-v_UPP_DataHigh and XDataHigh: 8 bits Data from DSP

    One can seen the same content is send 2 times3302.upptx.zip

    I start the UPP_TX transfer once pro some miliseconds, it's not possible that 2 transfers overlap in time

    I hope you can analyze and find the reason of that issue.

    Best regards

    Jan

  • 0 in reply to Jan Debiec
    TI__Mastermind 20790 points

    Jan,

    UPP DMA channel Q descriptor 1(UPQD1) register:
    This register used to program the line count per window and byte count per line for DMA Channel Q.
    The line count (LNCNT) may be set to any number from 1 to 65 535 (FFFFh).

    I hope, your understanding of line count and byte count are clear. Please double check the below register values are set.
    Line Count (UPxD1.LNCNT) – The number of lines per window.
    Byte Count (UPxD1.BCNT) – The number of bytes per line. The byte count must be an even number.
    Line Offset Address (UPxD2.LNOFFSET) – The offset address between the first byte in successive lines.
    The total number of bytes transferred equals B × L.


    Please check the below configuration also, If you are doing Single Data Rate (SDR) Interleave
    UPCTL.CHN = 0 (single-channel mode)
    UPCTL.DRA = 0 (single data rate)
    UPCTL.MODE = 1 (transmit mode)
    UPCTL.SDRTXIL = 1 (enable SDR transmit interleave)
    UPCTL.DDRDEMUX = 0 (disable DDR interleave)

  • 0 in reply to Pubesh
    Prodigy 170 points

    Hi Pubesh,

    Content of my registers:

    UPCTL = 0x02020006

    UPQD1 = 0x00010040

    UPQD2 = 0x00000040

    I'm not using interleave mode, my UPCTL settings:

    UPCTL.MODE = 0x2; DuplexMode, ChA = Rx, ChB = Tx

    UPCTL.CHN = 0x1; DualChn mode

    UPCTL.SDRTXIL = 0; disabled interleave mode

    UPCTL.DDRDEMUX = 0 disabled

    UPCTL.DRA = 0; SIngle data rate

    UPCTL.IWA = 1; 16 bits

    UPCTL..DPWA = 0; no data packing

    UPCTL.DRB = 0; single data rate

    UPCTL.IWB = 1 ; 16 bits

    UPCTL.DPWB = 0; no data packing

    YOu can see contens of register in a file: 140526_upp_regs.dat8308.140526_upp_regs.dat

    I have created with CCS-Command: SaveMemory from addr 0x0258-0000

    Best regards

    Jan