C6657 power on sequence clairification

David Tate

I am using the I/O before core power on sequence in my design and have the following question.

Document SPRS814 has a note in section 7.2.1.2 where TI reccomends a maximum of 100ms between one rail and the next. My design is using a rather large FPGA to control the DSP power on sequence. In this case the 1.8 volt I/O rail will be powered on for ~1.5 seconds while the FPGA boots then CVDD, CVDD1 and the DDR3 1.5V rails will be sequenced on.

Is this going to be an issue?

David

over 10 years ago

0 Bill Taboada over 10 years ago

TI__Mastermind 42545 points

David,

1.5 seconds doesn't meet the power sequencing requirement so it is an issue. We only guarantee operation if the requirements listed in the data manual are met.

Regards, Bill

0 David Tate over 10 years ago in reply to Bill Taboada

Prodigy 60 points

Bill,

Thanks for the response. The max 100ms between rail sequences is not a requirement in the data sheet. It is a reccomendation detailed in a note. I understand keeping the CVDD and CVDD1 rails close in time as stated in table 7-3. I would like to understand the reason for the reccomendation so I can make a design decision.

thanks,

David

0 Bill Taboada over 10 years ago in reply to David Tate

TI__Mastermind 42545 points

Hi David,

The power sequencing requirement is specified for the C6657 in section 7.2.1 of the data manual. These requirements were provided by the silicon designers and the part is tested with those limits in place. I can't speculate on the behavior of the C6657 if the power sequencing requirements are not followed since we don't test the part in conditions outside those provided by the designers.

Regards, Bill

0 David Tate over 10 years ago in reply to Bill Taboada

Prodigy 60 points

OK, thanks for your help. I am changing my design to comply.

David

Processors

Processors forum

C6657 power on sequence clairification