PCIe Link down when execute DMA write

jung jin jang

Prodigy 20 points

Other Parts Discussed in Thread: CDCE62005

I made a c6678 custom board with local 100MHz PCIe ref. clock.

This board and Host PC(linux) is connected and linked up successfully with separate ref. clocks. (2.5GT/s, x1)

But after DMA write to c6678 using HAL_writeDMA about 400kbytes, PCIe link down. (LTSSM value goes 0.)

How can I fix this problem ?

Below are our PCIe resister values.

PCIE_APP_SERDES_CFG0 : 0x62320

PCIE_APP_SERDES_CFG1 : 0x22320

PCIE_LINK_STAT_CTRL : 0x00110000

ps. Same case but common clock source, It works perfectly.

over 9 years ago

0 Ganapathi Dhandapani95 over 9 years ago

TI__Mastermind 28085 points

Hi Jung,

LINK_SPEED = 0x1 in PCIE_LINK_STAT_CTRL register, link initialization is GEN1 (2.5GT/s).

Read the MAX_LINK_SPEED bits on LINK_CAP register. If it is not 0x1, Writing 0x1 to LINK_CAP register will limit maximum link speed to 2.5Gbps(GEN1).

What is the frequency of separate ref. clock? Are you verify/probe the clock signal.

Thanks,

0 jung jin jang over 9 years ago in reply to Ganapathi Dhandapani95

Prodigy 20 points

Hi ganapathi,

PCIe ref. clock is 100MHz and zitter is under 70ppm. So I think it is not a clock problem.

Link with commicial main board is always Gen1(2.5GT/s).

Thanks.

Regards.

J.J.Jang

0 Ganapathi Dhandapani95 over 9 years ago in reply to jung jin jang

TI__Mastermind 28085 points

Hi Jang,

No need to modified the code in DSP side for separate/common ref. clock selection. Please probe and verify the PCIe ref. clock in separate clock mode at PCIe link down time.

In C6678 EVM PCIe ref. clock will be controlled by SW5[3] pin. FPGA code will control the MUX output based on SW5[3] pin.

PCIe mux control:

0 = PCIe reference clock from CDCE62005

1 = PCIe reference clock from AMC

Thanks,

0 Raja over 9 years ago in reply to Ganapathi Dhandapani95

TI__Guru* 81335 points

Any update. Please help us to close the thread.

Thank you.

0 Sachan Rao over 8 years ago

Prodigy 230 points

Hi Jung,

Did you resolve this issue? I am seeing my link go down as well. I am interfacing between an FPGA and a C6678.

Regards,
Sachan

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PCIe Link down when execute DMA write