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Missing LSU SRIO Interrupt (C6678)

Mark Samson
Intellectual 355 points

I'm using the SRIO for sending data from the DSP to a second DSP or a FPGA.

I have a core dedicate for the transmission that use all the 8 LSU.

In my code every LSU is dedicated to a different preset transaction so i can have up to 8 different transaction (I cannot use a unique LSU because i want to use a single SRCID and so i cannot identify transaction by SRCID) 

I'm using the WRITE transaction because i don't need to receive confirmation for reception of packets.

However, in my code i can have up to 8 outstanding transaction simultaneously and so i'm interested in a confirmation ot che completion of the transaction so i'm polling the  LSU1 Interrupt Status Register to see what LSU has completed the transaction and so identify correctly the transaction that have been completed.

The problem is that  LSU1 Interrupt Status Register is never set (and i know that the transaction are completed correctly because in LSU0 Interrupt Status Register the bit 0 is set telling me that SRCID0 transaction is completed with success.

So, what could be the problem? Why the LSU0 Interrupt Status Register don't reflect the status of the successfull completed transaction?

  • 0
    TI__Mastermind 28085 points

    Hi Mark,

    The LSU0 Interrupt Status Register has 32 SRCID based interrupt sources, 16 of which are good completion interrupts and the other 16 are bad completion interrupts. Similarly, LSU1 Interrupt Status Register has 8 LSU specific interrupt sources and each interrupt is associated with a LSU.

    If you need more information about LSU  Interrupt Status Register, Refer SRIO user guide.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 355 points

    I know, i've readen the datasheet.

    The fact is that LSU0 Interrupt Status Register is working correctly, if i trigger 3 transaction with srcid0-1-2 i see the correct bit in the register 0x029001C0 after the transaction.

    But, after the transaction completed successfully i don't see any bit setted in the LSU1 Interrupt status register, while i'm expeting to see '1' the bit representing the LSU used for the transaction, in my case LSU0.

    LSU1 Interrupt status register (0x029001D0) remain always 0 whatever LSU i use for transaction...

  • 0 in reply to Mark Samson
    TI__Mastermind 28085 points

    Hi Mark,

    LSU1_ICSR has 8 LSU specific interrupt sources and each interrupt is associated with a LSU. Each one of these interrupt sources have a corresponding ICRx (4 bits) configuration associated with it. This ICRx configuration specifies the interrupt routing to the different INTDSTs.

    Are you routed the LSU1 Interrupts to Interrupt Destination (INTDST0-INTDST15) in your code.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 355 points

    I've still no routed the interrupt, im polling the interrupt status register LSU1_ICSR and i see that the register remains 0 all the time

  • 0 in reply to Mark Samson
    TI__Mastermind 28085 points

    Hi Mark,

    If you are not routed the LSU1 interrupt to Interrupt Destination means the LSU1 interrupt is not enabled. Please route the LSU1 interrupt in your SRIO Interrupt init code (Route LSU1 ICRx to INTDSTx) and check the status.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 355 points

    I don't want to route the interrupt to the cores because i want to check these regs using polling.

    Where is written in the datasheet that i have to ruote the interrupt for enabling that register?

    Isn't LSU1_ICSR a register that shows if the interrupt condition has occurred, as LSU0_ICSR?
    And i'm able to see the correct values in LSU0_ICSR even without routing the interrupt.
    Should't be the same for LSU1_ICSR ?

  • 0 in reply to Mark Samson
    Genius 4165 points
    Hi Mark

    I have encountered the similar problem or missing LSU completion interrupt. Can you tell me how you solved this problem?

    Thanks
    Xining