Bill,
I just saw the newly revised 'DDR3 Design Requirements for KeyStone Devices Application Report' (SPRABI1B). It computes the min and max write-leveling skew requirements for the Keystone I (section 4.3.1.10). What, if any, are the equivalent the min and max skew requirements for Keystone II devices?
This document also computes the round-trip delay for Keystone I (4.3.1.9). What are the route-trip delay requirements for Keystone II devices?
thanks,
Scott