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Keystone II DDR3 write-leveling skew

Bill,

I just saw the newly revised 'DDR3 Design Requirements for KeyStone Devices Application Report' (SPRABI1B). It computes the min and max write-leveling skew requirements for the Keystone I (section 4.3.1.10).    What, if any, are the equivalent the min and max skew requirements for Keystone II devices?

This document also computes the round-trip delay for Keystone I (4.3.1.9).   What are the route-trip delay requirements for Keystone II devices?

thanks,

Scott

  • Hi Scott,

    We're in the process of adding the following text to the DDR3 Design requirements document for the KeyStone II devices.

    Regards, Bill

    Write Leveling Limit Impact on Routing – KeyStone II


    The write-leveling process in the DDR3 interface imposes a limit on the maximum and minimum skew between the command delay and the data delay. If these limits are exceeded, the DDR3 interface may fail the write leveling process and data corruption may occur. These limits are sufficiently large that well-controlled topologies will not likely exceed the limits.

    The command delay is defined as delay for the clock, command, control, and address group signals from the DSP to a given SDRAM. The data delay is the delay for the data group signals to that same SDRAM. The write-leveling result is effectively the difference, or skew, between these two delays.
    The maximum write-leveling skew is the largest difference between the two delays in the topology to a single SDRAM. Likewise, the minimum write-leveling skew is the smallest difference between the two delays in the topology to a single SDRAM. The write-leveling logic has an upper limit which is the lower of 1.75 clock periods or 2500 ps. For instance, when operating at 1600MT/s, the clock is 800MHz which has a period of 1250ps. The maximum skew is 1.75 clock periods or 2187ps. At a propagation delay of 180ps per inch, this limits the write-leveling routing skew length to just over 12.1 inches.
    The minimum write leveling skew occurs when the command delay is less than the data delay. The minimum write-leveling skew is 0.75 times the clock period. At 1600MT/s, this minimum skew is 937ps or about 5.2 inches. The DDR3 PHY implemented on KeyStone II can operate within these limits without the need to invert the clock to the DDR3 SDRAMs.


    Round-Trip Delay Impact on Routing – KeyStone II


    The leveling processes in the DDR3 interface impose an upper limit on the maximum round-trip delay. If this limit is exceeded, the DDR3 interface may fail the leveling process and data corruption may occur. This limit is sufficiently large that well-controlled topologies will not likely exceed the limit.
    The round-trip delay for a given SDRAM is defined as the sum of two delays. The first is the delay for the clock, command, control, and address groups to that SDRAM. The second is the delay for the data group to that same SDRAM. This round-trip delay must be calculated for each byte-lane to each SDRAM device implemented in the DDR3 memory topology. All of these individual sums must be below the limit to ensure robust operation.
    The DDR3 PHY logic has an upper limit of 6 clock cycles. For instance, when operating at 1600MT/s, the clock is 800MHz which has a period of 1250ps. The maximum round trip delay is 6 clock periods or 7500ps. At a propagation delay of 180ps per inch, this limits the maximum round trip routed length to over 41.6 inches.

  • Hi Bill,   

    Is another way to look at this as follows?   

    - The Command Delay can exceed the Data Delay by the 'maximum write-leveling skew'?  

    - The Data Delay can exceed the Command Delay by the 'minimum write-leveling skew'?

    Just want to be 100% clear.   Thanks.

    Scott.

  • Hi Scott,

    In very simple terms, that is true. Remember that both conditions must be true for every memory on the board. These numbers are pretty generous so we don't believe it should cause any problems.

    Regards, Bill

  • Dear Bill,

    We are having some confusion with respect to the minimum write leveling skew in DDR3-1066 in Keystone 1 and 2.

    As per the 'DDR3 Design Requirements for KeyStone Devices Application Report' (SPRABI1B May 2014) minimum write leveling skew is the smallest difference in signal length between ACC group signals and Data group signals to the same DDR chip. The equation to calculate this value is also mentioned. As per that equation for a speed of 1066Mhz operating speed we got a value of 2.36in. Does this mean that the smallest difference between the control group and data group signals should be minimum 2.36in ?
    Or, The Data Delay can exceed the Command Delay by the 'minimum write-leveling skew' of 2.36in.

    In our current design, Few ACCC signals are ground referenced and few are Power referenced. In few places a single ACCC signal is referenced with power in one layer and ground in another . Is it okay?

    Regards,
    Sivanantham.
  • Sivanantham,

    Please refer below thread for the answer to your query.

    e2e.ti.com/.../472907

    Regards,
    Senthil
  • Hi Sivanantham,
    The skew question has been addressed in other posts. Note that the skew requirement found in section 4.3.1.9 'Round-Trip Delay Impact on Routing' is only applicable to KeyStone I parts. KeyStone II does not have this requirement.
    ACCC signals can be reference to either a ground or to the DVDD15 voltage plane. It is acceptable to switch the plane that acts as a reference but decoupling caps between DVDD15 and ground should be placed near the vias used to transition the signals between the two routing layers. Ideally, ground would be used as a reference for all the ACCC signals in addition to the data signals but that is not always possible. Also note that the traces should not be routed across a break in the plane. If it is referenced to DVDD15, there must be a solid DVDD15 plane under that entire portion of the trace. If it is referenced to ground, there must be a solid ground plane under the entire portion of the trace.
    Regards,
    Bill
  • Dear Senthil,
    I m getting "Access denied" to download/view the item.

    Regards,
    Sivanantham
  • Hi Sivanantham,

    The post referenced was internal. I have copied my comments below.

    Your routing should meet both the minimum skew and the maximum skew to be valid. The 2.36 inches you listed looks like it a correct answer if the invert clock out state is disabled. If the skew between your command group and your data group is smaller then 2.36 inches you will have to check the conditions with the invert clock out state enabled

    Regards,

    Bill

  • Hi Sivanantham,
    It is also discussed in the following post.
    e2e.ti.com/.../1417948
    Regards,
    Bill
  • Hi Bill,

    I'm Dongho Yu who uses Keystone II.

    I have a question about your saying. You commented that KeyStone II does not have this requirement for Round-Trip Delay in the upper post.

    Is the same for Write Leveling? For KeyStone II, can I ignore the equations in section 4.3.1.10?

    If so, plz, check below contents for KeyStone II for confirming 100%.

    Maximum Write Leveling Skew

    DDR3-1333   2.5 ns(Invert Disabled)          2.5-0.75 = 1.75 ns(Invert Enabled)

    DDR3-1600   2.1875 ns(Invert Disabled)    2.1875-0.625 = 1.5625 ns(Invert Enabled)

    Minimum Write Leveling Skew

    DDR3-1333   1.125 ns(Invert Disabled)          1.125-0.75 = 0.375 ns(Invert Enabled)

    DDR3-1600   0.9375 ns(Invert Disabled)    0.9375-0.625 = 0.3125 ns(Invert Enabled)

    If upper contents are right, command delay should exceed data delay by more than 0.3 ns, even though I use clock inverted.

    That means that I should lengthen command delay more than data delay.

    This is right?

    I hope you check this for Keystone II.

    Best Regards,

    Dongho.

  • Hi, Bill

    Can I get your answer for my question related to Keystone II?

    I posted it as reply to your post 2 weeks ago.

    Thank you.

    Regards,

    Dongho.

  • Hi Dongho,

    I am confused by your question. At the beginning of this thread I posted the KeyStone II requirements for both write leveling delay and for round trip delay.  Section 4.3.1.10 is labeled as a requirement for KeyStone I. The calculations you provided appear to be associated with KeyStone I.

    Regards,

    Bill

  • HI, Bill.

    I arrange my question.

    As this question related to minimum write leveling is so important to me, plz, reply me.

    I state based on the DDR3 Design requirements document for the KeyStone II devices of your post(Jun 12, 2014 5:42 PM).

    Maximum Write Leveling Skew

    DDR3-1600   2.1875 ns(Invert Disabled)    

    Minimum Write Leveling Skew

    DDR3-1600   0.9375 ns(Invert Disabled)    

    If upper contents are right, command delay should exceed data delay by more than 0.9375 ns.

    That means that I should lengthen command delay more than data delay by at least 5.2inches as your post.

    This is right?

    If I understand right, although you say "without the need to invert the clock to the DDR3 SDRAMs", I need invert clock.

    I need minus writeleveling skew. 

    Am I not able to use invert clock in KeyStone II?

    I hope you check this for Keystone II.

    Thank you for your help.

    Best Regards,

    Dongho.

  • Hi Dongho,

    You have misinterpreted my statement. The Write Leveling Skew represents the difference between the arrival of the clock/command signals and the data signals.
    The maximum write leveling skew occurs when the command delay is greater than the data delay. This is normal for DDR3 typologies routed in a flyby manner.
    The minimum write leveling skew occurs when the command delay is less than the data delay.
    The difference between the command/address length and the data length falls into a range. The maximum delay is when the address/command is 12.1 inches longer than the data. As the difference in length between of the command/address and the data gets smaller it will continue to be within the acceptable range. This is true all the way to the point where the address/command and the data are the same length and the difference is zero.
    If the address/command length becomes less then the data length, we start moving towards the minimum. You are within an acceptable range until the data length becomes 5.2 inches longer than the address/command bus.

    Let me try and express it another way.

    If address/command length > data length then
    address/command length - data length must be < 12.1 inches
    If address/command length < data length then
    data length - address/command length < 5.2 inches

    Using these rules the invert clock is not needed with KeyStone II devices. Does that make it easier to understand?

    Regards,
    Bill
  • Hi Bill,

    Thank you for your clear comment.

    I misunderstood like below.

        5.2inches < address/command length - data length < 12.1inches

    Additionally I have one more question.

    Based on your comment, write leveling skew value can't be minus. 

    In below your comment, the value is always plus.

    =========================================================

    If address/command length > data length then
    address/command length - data length must be < 12.1 inches
    If address/command length < data length then
    data length - address/command length < 5.2 inches

    ==========================================================

    But in Table18 of sprabi1b_DDR3_Design_Requirements_for_Keystone_Devices document,

    when Invert Clock OUt State is enabled, Skew in ps is minus and Skew in inches is plus.

    What do those values mean?

    That just means that

    If address/command length < data length then
    data length - address/command length < 2.138 inches for DDR3-1333?

    Is it OK that I ignore minus sign in -385ps?

    For clearance, I need your reply.

    Thank you for your reply.

    Best Regards,

    Dongho.

  • Hi Dongho,
    Table 18 only pertains to KeyStone I devices. It is not relevant to your design.
    Regards,
    Bill
  • Hi Bill,

    I know that.

    But I also use Keystone I and I think your comment for Maximum/Minimum write leveling skew is applicable for Keystone I,also.

    So,please,explain about my question in related to minus minimum write leveling skew.

    In fact, this is quite confusing. So I think that your reply is also helpful to other users.

    Thank you.

    Regards,

    Dongho.