I2C RSFULL condition

Hi Oleg,

Looks like this is expected behavior. This will occur when the previously received data is not read. Please refer Table 3-4 too.

Thanks.

Hi Rajasekaran!

I don't read any data, I write only I2CMDR mode register to set RESTART condition and get RSFULL bit set. I don't understand how can be overrun condition set if I write only I2CMDR mode register.

Hi Rajasekaran!

Please tell me the difference between RSFULL and ICRDRDY bits in ICSTR register? Although Table 3-4 in sprugv3 user guide states the different behavior for them I see them set together after I write only I2CMDR register to set RESTART condition with READ bit. If I start to read data from EEPROM, both of these bits are set each time I want to read data byte.

Hi Oleg,

When the I2C is receiving data, the data will copied from receive shift register to receive data register. If the receive data register is full (not read) then shift register can not copy data to receive data register. Table 3-4, holds the status of both bits RSFULL & ICRDRDY.

11 RSFULL - Receive shift register full bit. RSFULL indicates an overrun condition during reception. Overrun occurs when the receive shift register (ICRSR) is full with new data but the previous data has not been read from the data receive register (ICDRR). The new data will not be copied to ICDRR until the previous data is read. As new bits arrive from the SDA pin, they overwrite the bits in ICRSR.
0 = No overrun is detected. RSFULL is cleared by one of the following events:
» ICDRR is read.
» The I2
C is reset (either when 0 is written to the IRS bit of ICMDR or when the DSP is reset).
1 = Overrun is detected.

3 ICRDRDY - Receive-data-ready interrupt flag bit. ICRRDY indicates that the data receive register (ICDRR) is ready to be read because data has been copied from the receive shift register (ICRSR) to ICDRR. The CPU can poll ICRRDY or use the RRDY interrupt request.
0 = ICDRR is not ready. ICRRDY is cleared by one of the following events:
» ICDRR is read.
» ICRRDY is manually cleared. To clear this bit, write a 1 to it.
» The I2
C is reset (either when 0 is written to the IRS bit of ICMDR or when the DSP is reset).
1 = ICDRR is ready. Data has been copied from ICRSR to ICDRR

Hi Rajasekaran!

Thanks for quoting sprugv3 I2C User Guide! I can read it without asking you. Please read my question very carefully and try to understand the problem I've posted about!

Hi Oleg,

Is it possible to probe and verify the I2C clock & data lines when you trigger RESTART condition? 

Thank you.

Hi Rajasekaran!

I don't try it. But if I ignore RSFULL bit and check ICRRDY bit only, then I read data from EEPROM without errors.

Hi everybody!

Are there any suggestions or comments from TI?

Can TI confirm or deny the problem I've described earlier?