PCIE Interface configuration for C6657

Hi Ram,

Please take a look at below link:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/349074/1223005.aspx#1223005

Thanks,

Hi,

i saw the link not much info i got. i have the example.

my questions

(1) why not i am able to write in 0x60000000? after writing into it then whether i can verify on my FPGA address

0x02000000 whether i got the data or not. First i am not able tor write on 0x60000000,which is PCIE data for DSP core.

(2) if i configure  OB=0x02000000, then can i configure inbound with random number IB = 0x90000000?

thanks,

Ram.

Hi Ram,

Please share your DSP and FPGA BAR configuration datails.

Take a look at below link:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/301001.aspx

Thanks,

Hi Ganapathi,

thanks for your email.

my board has C6657 DSP as RC and FPGA as EP. FPGA IP BAR 1  has 0x0200000 with 64MByte.

so i configure as follows:

DSP(RC) outbound address = 0x02000000 and BAR-MASK = 0x03FFFFFF as i have to map with 64MByte on my FPGA.

Inbound address i took as IB = 0x90000000(i don't know it is right in my case as i took a random number as i don't need now to write from FPGA to DSP. i am only interested to write from DSP to FPGA).please tell me if it is right?

After configuring PCIE registers.it shows PCIE link is up. but i can't able to write in the memory of 0x60000000;

i don't understand why not i am able to write on 0x60000000?

thanks,

Ram.

Hi,

so for testing i configured as like you.

In my setup DSP C6657 configured as RC and FPGA configured as EP. DSP BAR2 bar mask BAR-MASK = 0x03FFFFFF as i have to map with 64MByte.i hope this is little bit confusing, as i understood 256MByte = 0x0FFFFFFF; and 64 MByte = 0x03FFFFFF; but when i take also in my test 256MByte = 0x0FFFFFFF the PLL hangs. so i took only 64MByte.

DSP Inbound address is 0x90000000 and Outbound address is 0x60000000

FPGA Inbound address is 0x60000000 and Outbound address is 0x90000000

The PLL is power up and Link is up. still i am not able to write in 0x60000000.it shows zeros? and not able to write anything? shall i have to configure anywhere my pcie addresses?

thanks,

Ram.

Hi Ram,

Have you refer the MCSDK PCIe example project?

Please try to test the same setup with low bar mask value(4MByte or 1MByte).

Thanks,

Hi Ganapathi,

i tried to load the PCIE example as told by you. it shows also the link is up.but i can't able to write to the

address 0x6000000. i don't know whether it is a hardware problem or i have to configure else where the start and end addresses of PCIE.

thanks,

Ram.

Hi Ram,

In the PCIe sample example two DSP EVMs are used to test the PCIe driver. EVM 1 is configured as a Root Complex and EVM 2 is configured as End Point.

Once the PCIe link is established, the following sequence of actions will happen:

*  - EVM 1 sends data to EVM 2

*  - EVM 2 waits to receive all the data

*  - EVM 2 sends the data back to EVM 1

*  - EVM 1 waits to receive all the data

*  - EVM 1 verifies if the received data matches the sent data and declares.

This PCIe example code is not directly supported on your test setup. You need to modify the example project for your design. If you want more information, Please take a look at Readme.txt file(C:\ti\pdk_C6657_1_1_2_6\packages\ti\drv\pcie\example\sample\Readme.txt)

Thanks,

Hi,

(1) we already tested the same pcie example project with two EVM's. it worked well.

(2)i took the PCIE example project as i know this is dedicatedely written to test EVM'S , so i modified it then the link  up is shown. so principally it has the same result as i have with my DSP Program. but in both cases i can't able to write on 0x6000000;

thanks,

Ram.

Hi Ram,

Please share your DSP debug message log and LTSSM_EN bits in COMMAND_STATUS register and the LTSSM_STATE in DEBUG0 register for before linkup state and after linkup state.

Thanks,

Hi,

I configured as

/* Outbound Base Address for PCIe Master */
#define PCIE_OB_LO_ADDR_M    0x60000000
#define PCIE_OB_HI_ADDR_M    0
/* Inbound  Base Address for PCIe Master */
#define PCIE_IB_LO_ADDR_M    0x90000000
#define PCIE_IB_HI_ADDR_M    0
/* Outbound Base Address for PCIe Slave */
#define PCIE_OB_LO_ADDR_S    PCIE_IB_LO_ADDR_M
#define PCIE_OB_HI_ADDR_S    0
/* Inbound  Base Address for PCIe Slave */
#define PCIE_IB_LO_ADDR_S    PCIE_OB_LO_ADDR_M
#define PCIE_IB_HI_ADDR_S    0

#define PCIE_BAR_MASK            0x03FFFFFF

DSP Debug Message Log:

[C66xx_0] Configuring PCIe Serdes.
PCIe Power Up.
PLL configured.
Successfully configured Inbound Translation!
Successfully configured Outbound Translation!
Starting link training...
Link is up.

COMMAND_STATUS -> before PCIE Configuration 0x00000000

                                           After PCIE config and Link up 0x00000007(LTSSM_EN bit is 1)

DEBUG_0 ->before PCIE Configuration 0x00000000

                       After PCIE config and Link up 0x0300DB11

As DSP(RC) ->OB(0x2180200)  -> 0x60000001

                            0x2180300 ->0x00000001

but i can't able to write in 0x60000000 it shows zeros.

thanks,

Ram.

Hi Ram,

The registers are fine in DSP side.

I think issue on FPGA side. Have you validate the FPGA PCIe interface?

Hi,

thanks for the info. i will check from FPGA side.

second i have one more question regarding the DDR3 PLLM, PLLD factors

for DDR3 the output CLK diagram as shown follow.

if i have Reference CLK freq 312.5 MHz and DDR3 CLK expected is 666.5 MHz. what are PLLM and PLLD factors?

for Main PLL controller there is a table specified in the data sheet,what PLLM and PLLD values to be taken  for different reference CLK frequencies but there is no such thing for DDR3.

Thanks,

Ram.

I am not able to view your diagram. Please share the diagram via attachment.

0285.DDR3_PLLDiagram.docx

Hi Ram,

I am not expert on this topic. I will check with hardware team and get back to you.

Thanks,

Hi,

one more question from my side in the mean time.

i want to configure LAN configuration for my setup. do the TI offer any example project for LAN configuration like PCIE example project for PCIE configuration?

thanks,

Ram.

Hi,

here it seems  PCIE from FPGA side. may be bar configuration i done on EP(FPGA) is wrong.i am giving the following values.

As i read the 0x21801000 (vendor and Device ID)-> 8888104C as i took my DSP as RC and Configuration as Local,so vendor and Device ID seems fine and also 0x21801014(BAR1)->90000000 for RC seems fine.

But as i understood 0x21802000 is for remote device i.e in my case FPGA.

so 0x21802000(vendor and Device ID)->1319162F, it is also fine with our FPGA vendor and Device ID.

but when i see 0x21802014(BAR1) on EP(FPGA) side it shows zero. so i thought the BAR1 configuration is not properly done on EP(FPGA) side. my question is who has to configure BAR1 for EP side in my case as my EP is FPGA?

and also 0x2180200 and 0x2180300 areOB and IB. these registers are fine in my RC mode. how i can also see the values of OB and IB configured in EP(FPGA) side?

thanks,

Ram.

Hi Ram,

EP(FPGA) side code to be configure the BAR1. I think the issue on your FPGA BAR configuration. Please verify the FPGA side PCIe configuration registers.

Please take a look a look at section 2.8 PCIe Address Spaces on DSP PCIe user guide(SPRUGS6D).

Thanks,

Hi,

who has to configure the EP(FPGA) side code to be configure the BAR1? i have to do from DSP side or

the FPGA developer has to do from his side in the FPGA.do i have the access to the FPGA side PCIe configuration registers from DSP? then what are the addresses?

thanks,

Ram.

Hi Ram,

You need to configure the BAR1 on FPGA side pcie driver code.

Yes, you able to access the FPGA side PCIe config resisters from DSP. Please take a look a look at section 2.8 PCIe Address Spaces on DSP PCIe user guide(SPRUGS6D) for more detail.

Thanks,

Hi,

You need to configure the BAR1 on FPGA side pcie driver code

yes if i have to do, then which registers i have to set. now i am taking my DSP as RC and configuration as Local,so setting PCIE application registers and barconfig. But how to configure BAR1 for FPGA(EP)?please explain me in more detail.

thanks,

Ram.

Hi Ram,

DSP PCIe initalization sequence are clearly defined in user guide document. Please take a look at section 2.11 Operations on SPRUGS6D.

DSP(RC) initialization code not configure the FPGA(EP) side BAR configuration.

I dont know the FPGA side PCIe configuration steps.

Thanks,

Hi,

Please see the link, its the same question from other customers.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/308667.aspx

thanks,

Ram.

I have not worked on similar setup(DSP to FPGA). Also, I do not enough resources to re-produce your case.

Take a look at below thread

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/282303/985867.aspx#985867

Thanks,

Hi, 

i solved the PCIE problem. it's mainly coming from DSP side, as i have to configure FPGA as EP from DSP side.And also in the EP, enable memory decoder should be done.

by the way have you got any feed back from your colleagues regarding DDR3 PLL?

thanks,

Ram.

Hi Ram,

Thanks for your update.

DDR3 PLL calaulation

Thanks,