Hi all,
I am using XTCIEVMK2X EVM.
Developing environment is: CCS ver 5.4.0.00091; MCSDK Packages: 3_00_01_12
Bootmode: ARM SPI Little Endian mode.
For K2H EVM, we want to download the DSP image through ARM with the help of 'MPM' module. So, we are using DDR3 from start address 0xA0000000 and a length of 512 MB.
In DSP linker cmd file, DSP memory map using DDR3 external address starting from 0xA000 0000 to 0xBFFF FFFF.
Through MPAX (Memory Protection and Extension), DSP can map 32-bit address to 36-bit physical address space. But we are using ARM SPI boot mode and 'mpmcl' commands, now by default Linux (ARM) manages (up to 2GB memory) mapping from 32-bit address to 36-bit address, so we are not configuring any xmc table again from DSP side.
With single core i.e. core 0, we are able to work with DDR3 memory as required. No issues with single core and we are trying to extend it to other cores.
Now while implementing for other cores, we are observing memory conflict issues across two cores (core 0 and core 1) in the usage of DDR3.
Memory conflict issue means some of the variables updated in core 0 are reflecting in core 1 . We are expecting these variables should be initialized with zeros and should be update in core 1 as per code.
Both cores are accessing the DDR3 region from 0xB200 0000 to 0xB300 0000.
Can you please provide the answers for below questions ?
1. We are not using MPAX / XMC tables, so how DDR3 memory can be sharable among different cores ?
2. How can I divide DDR3 region (from 0xA000 0000 to 0xBFFF FFFF) as CACHEABLE or NONCACHEABLE / SHARED or PRIVATE blocks ?
Thanks in advance.
Best regards,
Rajanikanth.