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Access to different address of same DDR3 memory by mulitiple ARM Core PAC in 66AK2H14

Michi Yama
Guru 10030 points
Other Parts Discussed in Thread: 66AK2H14

Hi,

I have some questions regarding Keystone2 architecture.

Now, I see two technical documents. One is MSMC User Guide. Other one is 66AK2H14 data manual.

The following are my questions.

1)According to the MSMC User Guide,  MSMC has only one slave port (ARM CorePac Coherent Slave Port) for ARM CorePac. Also the port to DDR3 memory (MSMC EMIF Master Port) is only one. I think that these facts mean multiple ARM Cores can't access to the address of DDR3 memory access in same time even though the address is different.

Is my understanding right?

2) As to my understanding,  the route from ARM CorePac to DDR3 is the following.

ARM CorePac  -->  MSMC  -->  (MSMC EMIF Master Prot)  --> DDR3 EMIF ---> DDR3 memory

Are there any routes execept for the above? If there is, please let me know the route.

I appreciate your quick reply.

Best regards,

Michi

  • 0
    TI__Expert 6815 points

    Michi,

    1) This is not exclusive to ARM CorePacs. The MSMC module provides multiple slave ports for C66x and ARM cores,  and non-core masters to access the DDR3 EMIF endpoint. But all accesses are routed through the MSMC EMIF Master Port. Once the commands reach the DDR3 EMIF, they are queued in a command FIFO and undergo an arbitration process as outlined in the DDR3 Memory Controller Users Guide. The arbitration mechanism ultimately decides how the commands are executed sequentially. So in that sense, no two masters can issue commands that get executed at the same time.

    However, if the commands happen to be arrive at the FIFO in a particular order they can be executed efficiently (example, each Core issues reads to different banks that are already open)

    2)  Your understanding is correct. That is the only possible route.