• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Subscribers 102 subscribers
  • Views 641 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Is it the latest information about an errata advisory 3 for C6654/55/57?

j-breeze
Mastermind 7560 points

Hi Champs,

According to C6654/55/57 Errata (SPRZ381A), a workaround of advisory 3 mentions DDR3_CONFIG_REG_23 register as follows.

  o C6654/55/57 Silicon Revision 1.0 Silicon Errata [SPRZ381A]
    (http://www.ti.com/lit/pdf/sprz381)

    - Page 12

      Advisory 3  DDR3 Automatic Leveling Issue

        Workaround:

          ...To do this, leave the read data eye training enabled
          (leave bit 9 in DDR3_CONFIG_REG_23 = 0),

But the register is not available for C665x as below.

  o KeyStone DDR3 Memory Controller U/G [SPRUGV8D]
    (http://www.ti.com/lit/pdf/sprugv8)

    - Page 58

      Table 4-2 DDR3 PHY Leveling Registers (See device datasheet for base address)
                (Part 1 of 2)

        Offset : 460h
        Acronym: DDR3_CONFIG_23 (NA for TCI6614 and C665x devices)

So, I think the errata info is not the latest one. Can I get the latest errata?

Regards,
j-breeze

  • 0
    TI__Expert 6815 points

    j-breeze,

    Thanks for the catch. Devices other than C665x and TCI6614 have a single register (CONFIG_REG_23) that controls the read data eye training for all byte lanes. C665x and TCI6614 on the other hand allow individual control of each byte lane through registers (CONFIG_REG_52 through 55 and 60) and (CONFIG_REG_52 through 60) respectively. For C665x, the errata should say "leave the read data eye training enabled (leave bit 9 in DDR3_CONFIG_REG_52 through 55 and 60 = 0)".

    We will get the errata updated.

    For more details please see the Keystone I DDR3 intiialization app note (http://www.ti.com/lit/an/sprabl2b/sprabl2b.pdf)

  • 0 in reply to Aditya
    Mastermind 7560 points

    Aditya,

    Thank you for your prompt reply, and I'd like to make sure a little more about the errata that you are going to update. 

    I think TCI6614 advisory 17 is equivalent to C665x advisory 3, and the advisory 17 has three workarounds.
    So, the C665x errata will have the same three workarounds? 

    Thanks in advance for your cooperation.

    Regards,
    j-brreze

  • 0
    TI__Mastermind 28085 points

    Hi j-breeze,

    Please take a look at section: 3 Leveling Execution and 3.3 Full Automatic Leveling on KeyStone I DDR3 Initialization Application Report.

    http://www.ti.com/lit/sprabl2b

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Mastermind 7560 points

    Hi Ganapathi,

    Thank you for your infomation.

    I've had a look at the doc, but I'd like to know whether I can use the workaround #1 of TCI6614 advisory #17 to C665x or not.  The workaround uses Partial Automatic Leveling, not Full Automatic Leveling.

      o TCI6614 Silicon Revision 1.0, 1.1, 1.3 Silicon Errata [SPRZ370D, May14]
        (http://www.ti.com/jp/lit/pdf/sprz370)

        - Page 29

          Advisory 17  DDR3 Automatic Leveling Issue

            Workaround 1:

              ...This solution is functional on standard DDR3 fly-by layouts
              and is referred to as Partial Automatic Leveling. It has been
              validated for robust operation at DDR3-1333 when connected to
              either a UDIMM or with a discrete SDRAM implementation.

    Can I use the workaround to C665x?

    Regards,
    j-breeze

  • 0 in reply to j-breeze
    TI__Expert 6815 points

    j-breeze,

    You are right. The three workarounds for TCI6614 also apply to C665x devices (of course, DDR3_CONFIG_REG_56 through 59 do not apply to the latter).

  • 0 in reply to Aditya
    Mastermind 7560 points

    Hi Aditya,

    Thank you for your support.  It's really useful infomation.

    So, could you please let me know the update schedule of the C665x errata, If you have any? 

    Regards,
    j-breeze

  • 0 in reply to j-breeze
    TI__Expert 6815 points

    j-breeze,

    I do not have the update schedule as yet. I will post an estimate on thread when I get one. The text for the workarounds will be the same as TCI6614.