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TI DSP C6670 SRIO Gen 1 interface Issue Xilinx FPGA RAPID IO REV 2.2

Hi,

I am using TI DSP C6670 SRIO Gen 1 interface with Xilinx Vertex FPGA RAPID IO REV 2.2

C6670 PDK - pdk_C6670_1_0_0_11

SRIO GEN 1 REV
Rate :- 3.125 GBaud
Mode :- 1x
PortNo. Used:- 0 , IDLE1 used

 

Problem :- delayed syncronization between DSP and FPGA.

 

Upon debugging in the FPGA via chipscope tool , its observed that the

TO make the SRIO Link status HIGH ---->

The FPGA TX Port after PORT initialization transmits 15 Consecutive Character symbols and expectes on RX Port to receive 7 error free control symbols.

But RX Port is received to a constant character "4A4A4A4A" and there is no control symbols being seen in the RX Port which leads to FPGA SRIO Port to go LOW and again after some time when DSP sends the character sequence "BCFDFDFD" continuously then the FPGA Port goes HIGH but instantaneously FPGA RX port recieves the "4A4A4A4A" character sequence which leads to FPGA SRIO Port to LOW.

FPGA is continously transmitting characters sequence " BCFDFDFD" .

This behaviour leads to toggling of FPGA SRIO Port to LOW/HIGH.

 

Why DSP while sending the sequence "BCFDDFBC" instantaneously sends the "4A4A4A4A" which leads to reset on the syncronization procedure. ??

Does this mean that while syncronizing DSP had triggered RESET ?

 

Regards,

Manav

 

 

 

  • Hi Manav,

    I am working with expert to answer this post. Thank you for your patience.

  • Can you verify your VMIN setting?  See: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/196080/850001.aspx#850001


    The physical layer state machines are verified compliant and have been proven to work with Xilinx FPGAs many times, so I think you may have a marginal link causing bit errors and the port_ok to toggle.

    Regards,

    Travis

  • hi ,ti employee,

    I have the same problem with  Manav ,

    I have 6678 connect with fpga with srio.

    fpga:xc6vsx315t   srio ip 5.6 version

    srio:1x 2.5gbps

    port:0

    the phenomenon is :

    The FPGA TX Port after PORT initialization transmits "bcfdfdfd",but RX Port is received to a constant character "601e19e7" and the fpga rx port signal  "rxdisperr" value is 1 or 2 and the signal "rxnotintable" value is 3.

    both the  fpga and dsp are not link. 

    my dsp code is as follow:

    I change some code from the demo code in the path"c:\ti\pdk_c6678_1_1_2_5\packages\ti\drv\srio\device\device_srio_loopback.c"

    the follow are changes:

    1,

    I change loopback mode to nomal mode;

    2,

    I add the follow code :

    for(i=0;i<4;i++)

    {CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 0);  }

    3,

    add code the follow code:

    for (i = 0; i < 4; i++)

    {

    /* Set the PLM Port Silence Timer. */

    CSL_SRIO_SetPLMPortSilenceTimer(hSrio, i, 0x2);

    /* TODO: We need to ensure that the Port 0 is configured to support both

    * the 2x and 4x modes. The Port Width field is read only. So here we simply

    * ensure that the Input and Output ports are enabled. */

    CSL_SRIO_EnableInputPort(hSrio, i);

    CSL_SRIO_EnableOutputPort(hSrio, i);

    /* Set the PLM Port Discovery Timer. */

    CSL_SRIO_SetPLMPortDiscoveryTimer(hSrio, i, 0x2);

    /* Reset the Port Write Reception capture. */

    CSL_SRIO_SetPortWriteReceptionCapture(hSrio, i, 0x0);

    /*Set VMIN to 15 as recommended by this post:

    * http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/196080.aspx */

    CSL_SRIO_GetPLMPortVMinExponentConfig(hSrio, i, &vminExponentConfig);

    vminExponentConfig.vminExp = 15;

    CSL_SRIO_SetPLMPortVMinExponentConfig(hSrio, i, &vminExponentConfig);

    }

    I change my code follow the suggustions,but there is not effect ,it is still not link.

    I do some other test:

    1,

    I test dsp 2x with fpga 1x ,they can link 1x.and the fpga RX Port can received a constant character "bcfdfdfd".

    2,

    I connect the dsp 's 1x rx and dsp 's 1x tx with flying line .and the dsp can link and can send the nwrite to itself.

    I donot know why?

    Regards,

    jie wang.

     

  • jie wang75279 said:
    The FPGA TX Port after PORT initialization transmits "bcfdfdfd",but RX Port is received to a constant character "601e19e7"

    Can you clarify the data being exchanged in terms of K characters and SRIO control symbols.  Please decode this further.

    jie wang75279 said:
    fpga rx port signal  "rxdisperr" value is 1 or 2 and the signal "rxnotintable" value is 3.

    I'm not familiar with the FPGA debug registers.  What are the DSP register status besides the no Port_ok?  What are the errorred states?  Did you try running the debug gel (http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/264325/927003.aspx#927003)?

    jie wang75279 said:

    1,

    I change loopback mode to nomal mode;

    Ok.

    jie wang75279 said:

    2,

    I add the follow code :

    for(i=0;i<4;i++)

    {CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 0);  }

    Not needed.  There is only one path register for the Keystone devices.

    jie wang75279 said:

    3,

    add code the follow code:

    for (i = 0; i < 4; i++)

    {

    /* Set the PLM Port Silence Timer. */

    CSL_SRIO_SetPLMPortSilenceTimer(hSrio, i, 0x2);

    /* TODO: We need to ensure that the Port 0 is configured to support both

    * the 2x and 4x modes. The Port Width field is read only. So here we simply

    * ensure that the Input and Output ports are enabled. */

    CSL_SRIO_EnableInputPort(hSrio, i);

    CSL_SRIO_EnableOutputPort(hSrio, i);

    /* Set the PLM Port Discovery Timer. */

    CSL_SRIO_SetPLMPortDiscoveryTimer(hSrio, i, 0x2);

    /* Reset the Port Write Reception capture. */

    CSL_SRIO_SetPortWriteReceptionCapture(hSrio, i, 0x0);

    /*Set VMIN to 15 as recommended by this post:

    * http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/196080.aspx */

    CSL_SRIO_GetPLMPortVMinExponentConfig(hSrio, i, &vminExponentConfig);

    vminExponentConfig.vminExp = 15;

    CSL_SRIO_SetPLMPortVMinExponentConfig(hSrio, i, &vminExponentConfig);

    }

    I change my code follow the suggestions,but there is not effect ,it is still not link.

    I do some other test:

    I would not advise changing the silence and discovery timer values and the number you use to very small.  The timers are affected by scalar registers, please see the following for explanation that is not in the SRIO user's guide yet: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/282116.aspx?pi303753=1

    Basically, when you can't get port_ok, it means that something is physically wrong, i.e. wrong data rate, refclk out of spec, bad connection or board routing, etc.  Your serdes config may not be set up correctly.  The gel might help pin point the issue, but you may want to look at your Serdes settings and look at: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/255031.aspx

    Regards,

    Travis