Hi,
I am using TI DSP C6670 SRIO Gen 1 interface with Xilinx Vertex FPGA RAPID IO REV 2.2
C6670 PDK - pdk_C6670_1_0_0_11
SRIO GEN 1 REV
Rate :- 3.125 GBaud
Mode :- 1x
PortNo. Used:- 0 , IDLE1 used
Problem :- delayed syncronization between DSP and FPGA.
Upon debugging in the FPGA via chipscope tool , its observed that the
TO make the SRIO Link status HIGH ---->
The FPGA TX Port after PORT initialization transmits 15 Consecutive Character symbols and expectes on RX Port to receive 7 error free control symbols.
But RX Port is received to a constant character "4A4A4A4A" and there is no control symbols being seen in the RX Port which leads to FPGA SRIO Port to go LOW and again after some time when DSP sends the character sequence "BCFDFDFD" continuously then the FPGA Port goes HIGH but instantaneously FPGA RX port recieves the "4A4A4A4A" character sequence which leads to FPGA SRIO Port to LOW.
FPGA is continously transmitting characters sequence " BCFDFDFD" .
This behaviour leads to toggling of FPGA SRIO Port to LOW/HIGH.
Why DSP while sending the sequence "BCFDDFBC" instantaneously sends the "4A4A4A4A" which leads to reset on the syncronization procedure. ??
Does this mean that while syncronizing DSP had triggered RESET ?
Regards,
Manav