System reset for hyperlink on DSPC8681

Adding further details:

/* Turn on the Hyperlink power domain */
if (CSL_PSC_getPowerDomainState (CSL_PSC_PD_HYPERBRIDGE) != PSC_PDSTATE_ON) {
/* Enable the domain */
CSL_PSC_enablePowerDomain (CSL_PSC_PD_HYPERBRIDGE);
/* Enable MDCTL */
CSL_PSC_setModuleNextState (CSL_PSC_LPSC_HYPERBRIDGE, PSC_MODSTATE_ENABLE);
/* Apply the domain */
CSL_PSC_startStateTransition (CSL_PSC_PD_HYPERBRIDGE);
/* Wait for it to finish */
while (! CSL_PSC_isStateTransitionDone (CSL_PSC_PD_HYPERBRIDGE));
}

The code snippet above is used in the hyperlink example project in the PDK to power up the hyperlink module.

The condition

if (CSL_PSC_getPowerDomainState (CSL_PSC_PD_HYPERBRIDGE) != PSC_PDSTATE_ON)

is satisfied only when system reset is done through CCS.

If the condition is bypassed, then the MCSDK application behaves randomly and it hangs. All further deskop linux resets fail and the system has to be rebooted.

Also if I do the system reset through CCS when using deskop linux, the PCIe link gets broken and the desktop linux reset fails.

Can you describe in your usage with desktop Linux, how do you do reset?

In CCS load case, after system reset via CCS, the GEL file will turn Hyperlink on from PSC domain, what inside the code to check Hyperlink domain will not be satisfied.

If the condition is bypassed, =====> how do you do this? Is Hyperlink powered on?

You can't do system reset through CCS when using desktop linux, because PCIE is also got reset and the communication with Linux machine will be lost.

From what I understood, you are trying to use desktop Linux to download some Hyperlink test code into DSP, and you had trouble in power on Hyperlink in the code, is that correct?

Regards, Eric

lding said:

From what I understood, you are trying to use desktop Linux to download some Hyperlink test code into DSP, and you had trouble in power on Hyperlink in the code, is that correct?

Yes. You are correct. My application is mcsdk.

lding said:

Can you describe in your usage with desktop Linux, how do you do reset?

I use the reset_dsp.sh which in turn uses the binary dsp_utils.

lding said:

If the condition is bypassed, =====> how do you do this? Is Hyperlink powered on?

I just commented out the if condition. I am not sure how to ascertain that hyperlink is powered on.

Basically I wanted to know how to turn on hyperlink when using desktop linux.

I added the line and rebuilt the SDK.

Now hyperlink is powering up.

I am verifying the hyperlink power up by doing reset through desktop linux and loading the example project through JTAG without reset.

For the first time after reboot in this method everything is working fine. But after running the example once, if I try reset again through desktop linux, these prints are coming up and the example project doesn't work afterwards:

Iterations waited for entry point to clear 1
Dsp 0: DSP Reset success !

setPscState: dsp_id 1: Previous transition in progress pid 5 mid 12 state: 0

setPscState: dsp_id 1: Current transition in progress pid 5 mid 12 state: 0

setPscState: dsp_id 1: MD stat for pid 5 mid 12 expected state: 0 state: 10 timeout

setPscState: dsp_id 1: Previous transition in progress pid 5 mid 12 state: 3

setPscState: dsp_id 1: Current transition in progress pid 5 mid 12 state: 3

setPscState: dsp_id 1: MD stat for pid 5 mid 12 expected state: 3 state: 10 timeout

Iterations waited for entry point to clear 1
Dsp 1: DSP Reset success !

Iterations waited for entry point to clear 1
Dsp 2: DSP Reset success !

setPscState: dsp_id 3: Previous transition in progress pid 5 mid 12 state: 0

setPscState: dsp_id 3: Current transition in progress pid 5 mid 12 state: 0

setPscState: dsp_id 3: MD stat for pid 5 mid 12 expected state: 0 state: 10 timeout

setPscState: dsp_id 3: Previous transition in progress pid 5 mid 12 state: 3

setPscState: dsp_id 3: Current transition in progress pid 5 mid 12 state: 3

setPscState: dsp_id 3: MD stat for pid 5 mid 12 expected state: 3 state: 10 timeout

Iterations waited for entry point to clear 1
Dsp 3: DSP Reset success !
Number of devices: 4
Device: 0 : dspc8681

boot config file initcfg_1250.txt
DSP boot config addr 0x86ff00
DSP boot config size in bytes 8
Boot config words: 0xbabeface,
Boot config words: 0x19,
Overriding image entry point with input 860000 Download image success !
Device: 1 : dspc8681

boot config file initcfg_1250.txt
DSP boot config addr 0x86ff00
DSP boot config size in bytes 8
Boot config words: 0xbabeface,
Boot config words: 0x19,
Overriding image entry point with input 860000 Download image success !
Device: 2 : dspc8681

boot config file initcfg_1250.txt
DSP boot config addr 0x86ff00
DSP boot config size in bytes 8
Boot config words: 0xbabeface,
Boot config words: 0x19,
Overriding image entry point with input 860000 Download image success !
Device: 3 : dspc8681

boot config file initcfg_1250.txt
DSP boot config addr 0x86ff00
DSP boot config size in bytes 8
Boot config words: 0xbabeface,
Boot config words: 0x19,
Overriding image entry point with input 860000 Download image success !

Did I miss something?

Thanks and Regards,

Shashikantha

The symptom looks that the Hyperlink can't be power off, stuck in PSC transition when you run the second time. So in your Hyperlink application code which runs on DSP core, you need to clean it up after running.

Regards, Eric 

Can you please detail the cleanup needed for the subsequent reset to work.

Do you mean adding code :

/* Turn off the hyperlink power domain */
if (CSL_PSC_getPowerDomainState (CSL_PSC_PD_HYPERBRIDGE) != PSC_PDSTATE_OFF) {
CSL_PSC_disablePowerDomain (CSL_PSC_PD_HYPERBRIDGE);
CSL_PSC_setModuleNextState (CSL_PSC_LPSC_HYPERBRIDGE, PSC_MODSTATE_DISABLE);
CSL_PSC_startStateTransition (CSL_PSC_PD_HYPERBRIDGE);
while (! CSL_PSC_isStateTransitionDone (CSL_PSC_PD_HYPERBRIDGE));
} else {
System_printf ("Power domain is already disabled.\n");
}

to turn off hyperlink?

Also when running through desktop linux, the DSP core may end its execution at different unknown points.

Can this be taken care of through desktop linux instead of the DSP? 

I have some code snippet, you can write your own for this sequence:

 /*disable all portal or remote register operation
 This bit should be set before iloop or reset bits are changed.*/
 hyperLinkRegs->CTL |= CSL_VUSR_CTL_SERIAL_STOP_MASK;

 /*Wait until no Remote Pending Request*/
 while(hyperLinkRegs->STS&CSL_VUSR_STS_RPEND_MASK);

 /*Reset*/
 hyperLinkRegs->CTL |= CSL_VUSR_CTL_RESET_MASK;

Then, your PSC code to turn Hyperlink off. Similar code can be seen in hyplnkReset() in ti\pdk_keystone2_3_00_04_18\packages\ti\drv\hyplnk\example\common for K2H device.

You shall try this sequence in CCS load to make sure it works. That is, after the first run. The code should be able to turn Hyperlink off, then your do a DSP core reset in CCS (not system reset), reload your code, it can run for the next time. If it is, this sequence can also work when load via PCIE/desktop linux.

"Also when running through desktop linux, the DSP core may end its execution at different unknown points.

Can this be taken care of through desktop linux instead of the DSP?"

Don't understand you question exactly, wouldn't code exit after running the test? If you need to reset the local DSP core, you can also do that via PCIE.

Regards, Eric 

In the mcsdk the application which uses the DSP, the DSP may run into errors and perform an exception and hang. In such scenario we will do reset from desktop linux and rerun the application with different parameters, with out rebooting the DSP.

So, when using hyperlink, how can I ensure that hyperlink powers up even if no hyperlink reset is done previous iteration where it was used?

Can the desktop linux reset the hyperlink and power it on?

If I add 

 hyperLinkRegs->CTL |= CSL_VUSR_CTL_SERIAL_STOP_MASK;

while(hyperLinkRegs->STS&CSL_VUSR_STS_RPEND_MASK);

hyperLinkRegs->CTL |= CSL_VUSR_CTL_RESET_MASK;

these lines in dnldmgr_reset_dsp() and reset these registers via PCIe then the hyperlink power up should be fine right? Regardless of the execution of the above code by the dsp?

That's right. You can either do this sequence in DSP code, or do this inside the download manager via PCIE.

Regards, Eric

Hi lding,

I am trying to read the hyperlink control register in dnldmgr_reset_dsp function as:
do_reg_read(dsp_id, (CSL_MCM_CONFIG_REGS + 0x04));
When executed, the getMemRegion which is called by pciedrv_dsp_read throws ERROR: pciedrv_dsp_read: Memory address out of range.
It seems only L2 ram, DDR and chip config space addresses are mapped in PCIe.
I added the line
ti667x_ep_setup_bar(i, 0, TI667X_EP_HYPER_BASE);
Where TI667X_EP_HYPER_BASE is CSL_MCM_CONFIG_REGS, in the pciedrv_open function.
Also added
if(is_in_hypercfg(dsp_addr, size))
{
bar_num = 0;
return(bar_num);
}
in getMemRegion().
Now do_reg_read is not throwing error, but the register values are not being read.
How to read the hyperlink control register through PCIe?

Thanks and Regards,
Shashikantha

When PCIE card is enumerated, please check how many BAR is assigned, maximum is 6 BAR. BAR0 is dedicated, but you can use any BAR 1-5. For example, there is a code to access EDMA confiuration:

    bar_num = getMemRegion(dsp_id, EDMA_TPCC0_BASE_ADDRESS, EDMA_ACCESS_MAX_OFFSET );

You could do the same for Hyperlink (0x2140_0000) region.

Regards, Eric

I am getting error:

pciedrv: Error in ti667x_ep_init_bar, ib trans num 4!, ret = -2
pciedrv: Found: IB_BAR = 00000000, IB_START_LO = 00000000, IB_START_HI = 00000000
pciedrv: Expected: IB_BAR = 00000005, IB_START_LO = 00000000, IB_START_HI = 00000000.
pciedrv: Error in ti667x_ep_setup_bar, ib trans num 4!, ret = -1
pciedrv: Found: IB_BAR = 00000000, IB_OFFSET = 00000000.
pciedrv: Expected: IB_BAR = 00000005, IB_OFFSET = 21400000.

I added

/* For hyperlink register configuration */
ti667x_ep_init_bar(i, 5);
ti667x_ep_setup_bar(i, 5, TI667X_EP_HYPER_BASE);