• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 101 subscribers
  • Views 383 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Questions about connecting c6670 to Xilinx FPGA using AIF2.

Sun-Gu Lee
Prodigy 210 points

Hi

we are testing in connection between c6670's AIF2 and Xilinx CPRI IP core.

(Xilinx Fpga is set to a slave and c6670 is considered as a master.)

at first try, link(frame sync) status was abnormal in c6670. (maintains "unsync" status)

but  we got "FRAMESYNC" status by connecting FPGA's recoverd clock(30.74MHz) to DSP(6670)'s PHYSYNC pin and RADSYNC pin.

here are questions.

1. Shoud PHYSYNC & RADSYNC pin requisitely be connected with FPGA??

Aren't AIF2 able to work properly with just only AIF2 differential Tx/Rx connection without any other connection with the opposite device.(like 6670's PHYSYNC pin)?

2. generally, What is a typical shape of AIF2's physical connection with counterpart device?

3. Can you give me any hints about software configurations  as a 2nd question's answer, if possible.

thanks in advance.

Lee

  • 0
    TI__Expert 4740 points

    Hi,

    in your case, the AIF2 Tx,Rx SERDES lane is connected with FPGA SERDES. used to generate Tx clock. this is normally how BTS and Radio head can be synchronized.

    However, if your FPGA is on the same board and the FPGA has real connection with Radio module, then your FPGA doesn't need to have clock recovery feature, because you can share the common clock source between DSP and FPGA. with this approach, both DSP and FPGA clock can be fully synchronized and you don't need to worry about frame data drift from jitter.

    In addition to this, you may need AIF2 timer sync pulse from DSP (PHYSYNC or RADSYNC pin) and this sync pulse will be used to start AT timer in AIF2 and also deliver correct radio timing to FPGA (FPGA timer also start with this signal) this is 10 ms periodic or one time signal and it can not be used as a clock source.

    I'm not sure why you connected your clock source to the sync signal pins of DSP. normally just one time pulse or 10 ms periodic pulse is enough for those pins.

    Regards,

    Albert

        

  • 0 in reply to Albert Bae
    Prodigy 210 points

    thanks for your response. albert.

    for your information, we are using seperate boards.

    If so, The pins like PHYSYNC or RADSYNC are just associated with only radio framing sync and Tx(egress) timer

    and they have nothing to do with CPRI frame sync operation.

    1. Am I right?

    We are using a DIO mechanism in AIF2 and we wanted that first IQ data in l2sram is loaded in CPRI Hyper frame boundary.

    when we started the AIF2 WCDMA example, IQ data in l2ram were loaded in any CPRI basic frame location of a Hyper frame , Ironically, before that we connect 30.74mhz from FPGA to DSP pins(PHYSYNC, RADSYNC).they didn't be syncronized in even K28.5 sync without above 30.74mhz connections.

    according to our fpga engineer, FPGA had a slave setting and clock recovery was in a activated status.

    2. Do you have any opinion about that?

    thanks.

  • 0 in reply to Sun-Gu Lee
    TI__Expert 4740 points

    Hi,

    if your FPGA is in different board, that means your FPGA has Rx clock recovery feature and it detects incoming CPRI from DSP and adjust clock cycle based on the incoming data clock cycle and it needs to be re-used for FPGA Tx module clock for perfect clock synchronization.

    PHYSYNC and RADSYNC is an activation pulse of AIF2 timer for CPRI and radio timing. for WCDMA and LTE, it has 10ms frame duration and both phy and rad timer generates 10 ms frame boundary signal and both signal perfectly matches without having any offset.

    I still don't understand why you used 30.74MHz clock output as a PHYSYNC input. as I told you in the previous reply, 10ms periodic pulse or just one time pulse is enough to activate AIF2 timers and you don't need to feed high frequency clock output to those pins.

    in conclusion, both PHYSYNC and RADSYNC is closely related with CPRI frame sync operation.

    for your second question, WCDMA first IQ sample should be loaded in the first CPRI basic frame in certain frame.

    On egress for downlink operation, AIF2 protocol encoder will start loading IQ data from the CPRI frame boundary, if you didn't set any AxC offset from MMR, so there is no garbage or zero data insertion for any basic frame.

    If you still don't understand what I have explained above, we'd better have a one hour conf call to make clear this.

    I can setup a call on 9 or 10 AM Thursday (korea time), 7 or 8 PM Wednesday (Houston time),  if you want and let me know which time slot is good to you.(I'll check email tonight)

    Regards,

    Albert