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UPP ENABLE signal in transmit mode

dave k
Intellectual 305 points

We are using the UPP bus on the C6655 interfaced to an FPGA.  We have set channel B up in transmit mode and set bit 28 of UPICR to 1 and bit 17 to 0.  This should program the Enable signal to be active high and change on the falling edge of the clock.  We are seeing the Enable signal go high 4 ns after the falling edge of the clock but the Enable signal goes low approximately 8 ns after the rising edge of clock.  We are running at 18.75 MHz.  I have attached logic analyzer screen shots of the falling edge of the Enable signal.  Do you know why the Enable signal is going low off the rising edge of the clock?

  • 0
    TI__Mastermind 20790 points

    Dave,

    If you are setting 1 for CLKINVB, the clock is inverted and Channel B signals align on falling edge of clock.
    If you are setting 0 for ENAPOLB, the enable is active-high for Channel B.

    The ENABLE signal is active-high by default, but its polarity is controlled by the ENAPOLx bit in UPICR.
    In transmit mode, ENABLE is an output signal and is always driven.
    In receive mode, ENABLE is an input signal and may be disabled using the ENAx bit in UPICR.

    Refer the section "Step-by-Step Procedure" for how to program the uPP configuration registers at UPP user guide.

    Can you share rest of UPP configured register values to validate?

  • 0 in reply to Pubesh
    Intellectual 305 points

    Here are our register settings

    UPP_UPPID = 0x44231100
    UPP_UPPCR = 0x00000008
    UPP_UPDLB = 0x00000000
    UPP_UPCTL = 0x02020006
    UPP_UPICR = 0x39383938
    UPP_UPIVR = 0xaaaabbbb
    UPP_UPTCR = 0x03030303
    UPP_UPISR = 0x00000000
    UPP_UPIER = 0x00000000
    UPP_UPIES = 0x00001f1f
    UPP_UPIEC = 0x00001f1f
    UPP_UPEOI = 0x00000000
    UPP_UPID0 = 0x00000000
    UPP_UPID1 = 0x00000000
    UPP_UPID2 = 0x00000000
    UPP_UPIS0 = 0x00000000
    UPP_UPIS1 = 0x00010000
    UPP_UPIS2 = 0x00000020
    UPP_UPQD0 = 0x00000000
    UPP_UPQD1 = 0x00000000
    UPP_UPQD2 = 0x00000000
    UPP_UPQS0 = 0x00000000
    UPP_UPQS1 = 0x00010000
    UPP_UPQS2 = 0x00000020

  • 0 in reply to dave k
    TI__Mastermind 20790 points

    Dave,

    I did not find any major issue in the configured register values. But I need to conform with you for the UPP_UPICR = 0x39383938 value. From that, are you using or configured for Chennal A ?  

  • 0 in reply to Pubesh
    Intellectual 305 points

    We are using Channel B as the transmit from the DSP to the FPGA and Channel A as the transmit from the FPGA to the DSP.

  • 0 in reply to dave k
    TI__Mastermind 20790 points

    Dave,

    Thanks for the update, If possible share your piece of code to investigate and provide technical suggestion. 

  • 0 in reply to Pubesh
    Intellectual 305 points

    Pubesh

    Here is our code.

  • 0 in reply to dave k
    Intellectual 305 points

    Bill from TI answered my question.  Thanks.