Hi,
I'm having a problem with C6670.
In customer board, if core clock is configure to 1GHz, the operation of DSP becomes unstable.
But if the clock is under 1GHz(ex.983MHz), the operation is stable.
I have a few questions in relation to this problem.
1.
In evmc6670l.gel file, the Device Speed are set to 983MHz for default.
Is there any reason Device Speed is set as 983 MHz instead of 1 GHz, in EVM?
2.
In evmc6670l.gel line.77 there are comment about PLL1_M as follow:
"Please select PLL1_M values such that 0 < PLL1_M <= 64"
Is there a limitation for setting PLL1_M?
When values other than this limit value are set up, does any problem occur?
I can't find this limitation from Keystone PLL User Guide and C6670 datasheet.
My understanding is that it can set up by the number of bits of a PLLM register.
best regards,
g.f.