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C6670 Device Speed Limitation

Guru 15510 points

Hi,

I'm having a problem with C6670.

In customer board, if core clock is configure to 1GHz, the operation of DSP becomes unstable.
But if the clock is under 1GHz(ex.983MHz), the operation is stable.

I have a few questions in relation to this problem.

1.
In evmc6670l.gel file, the Device Speed are set to 983MHz for default.
Is there any reason Device Speed is set as 983 MHz instead of 1 GHz, in EVM?

2.
In evmc6670l.gel line.77 there are comment about PLL1_M as follow:
"Please select PLL1_M values such that 0 < PLL1_M <= 64"

Is there a limitation for setting PLL1_M?
When values other than this limit value are set up, does any problem occur?
I can't find this limitation from Keystone PLL User Guide and C6670 datasheet.
My understanding is that it can set up by the number of bits of a PLLM register.

best regards,
g.f.

  • G.F.

    I'm not sure why the GEL file was programmed this way, but it's not a limitation with the PLLM.  There's no limitations here, any PLLM/PLLD configuration that gives you a valid operating frequency will work.  You can adjust the values to make it closer to 1GHz if you chose.

    Best Regards,

    Chad.

  • Hi G.F.,

    The device speed was set to 983.04MHz because of the reference SYSCLK frequency used was 122.88MHz. While you can get closer to 1GHz using a larger divider value, the 982.04MHz used was considered acceptable for the EVM. What multiplier and divider values did you use to get the unstable 1GHz core clock?

    Regards, Bill

  • Hi Chad and Bill,

    Thank you for the reply.

    Actually this problem occured at my customer.
    So, I will ask to them about the PLLM and PLLD value.
    I will be back to this post as soon as possible.

    I'm sorry but I have one more question to make me sure.
    I found the Note about PLLM at PLL user guide(sprugv2f) as follow:
    *********************************************************
    4.4 PLL Multiplier Control Register(PLLM)

    Note- Table 4-4 lists all the possible values for the PLL multiplier bits (PLLM).
    However, some of these values may not be valid for your particular device. For
    a list of valid values for PLLM, see the device-specific data manual.
    **********************************************************

    There was no list of valid values for PLLM in C6670 data manual.
    So, I understood as we can set PLLM[12:6] and PLLM[5:0]
    in MAINPLLCTL0/PLLM register to any value for C6670. Is it correct?

    best regards,
    g.f.

  • Hi Bill,

    Our customer are using 156.25MHz reference clock and
    they are setting the PLLM and PLLD as follow to generate 1GHz :
    ***********
    PLLM = 63
    PLLD = 4
    ***********

    best regards,
    g.f.

  • Hi g.f.,

    Those values should be valid for the C6670 if a 156.25MHz clock is used. Are they using the ALTCORECLK input for the reference clock?

    Regards, Bill

  • Hi Bill,

    Thank you for the reply and I'm sorry for the delay.

    They are not using ALTCORECLK input.
    Using SYSCLK as reference clock.

    best regards,
    g.f.

  • Hi G.F.

    156.25MHz is not a valid frequency for SYSCLK. In the C6670, SYSCLK is used as a source for both the main PLL and the AIF2 serdes interface. The AIF2 requires one of three specific reference clock frequencies for proper operation which include 122.88MHz, 153.6MHz or 307.2MHz, as specified in the C6670 data manual. If you are using a 156.25MHz clock for SYSCLK than the AIF will not operate correctly. Since you are not using the AIF, I would expect ALTCORECLK to be used as the source for the main PLL or I would expect you to be using a KeyStone I variant without the AIF2 such as the C6678. Have I misinterpreted the information you've provided?

    Regards, Bill

  • Hi Bill,

    Thank you for the details.

    In customer board, ALTCORECLK(P/N) pins are connected to POWER and GND.
    So that it's impossible to use as reference clock.

    In C6670 data manual(sprs689d) page.141, there is explanation as follows:
    ********************************************************************************
    2 If AIF2 is being used then SYSCLK(N|P) can be programmed only to fixed values,
    if AIF2 is not being used then any value in the range between the min and max values can
    be used.
    ********************************************************************************

    The customer are not using AIF so that isn't 156.25MHz valid frequency for SYSCLK?
    If not valid, do they must input 122.88MHz/153.6MHz/307.2MHz to SYSCLK and
    generate Core CLK closer to 1GHz?
    The customer are using Turbo/Viterbi coprocessor so that they need to use C6670.

    best regards,
    g.f.

  • Hi G.F.

    If the AIF is not used than the 156.25Mhz should be fine. My concern is that it doesn't meet the requirements for SYSCLK under timing. I'll check with the specification owner to see if there are any hidden concerns.

    Regards, Bill