Questions about SRIO (C6678)

Gabriele_Giannini

I've some questions about SRIO peripheral and the order of output transaction.
I'm using a singole Core for the SRIO bus access and all the 8 LSu are dedicated to that core.
I'm using DIRECT-IO transactions

Have all the lsu the same priority?
If I write in the shadow reg more Write consecutive transactions with the same priority, will these be carried out with a FIFO order? Or the peripheral make some optimization depending on the bytecount of the transactions?
If i prepare in the shadow regs a Read transaction and next a Write transaction, will the LSU trigger the write transaction immediately after the read request, or only after receiving the read response with payload?
If i trigger a Read transaction ad i request a completion interrupt, when will the interrupt be trigger? After the LSU has sent the request or after the MAU has received the payload?
If i'm servicing a doorbell interrupt or a LSU interrupt and while i'm in the ISR another transaction is completed, whill the new interrupt be triggered and a new interrupt service routine called or not?

over 9 years ago

0 Ganapathi Dhandapani95 over 9 years ago

TI__Mastermind 28085 points

Hi Gabriele,

Ans1: Yes it is possible, You need to set equal priority to each LSU.

Ans2: It carried out by FIFO order.

Ans3: The LSU cannot be released until the response packet is routed back to the module and appropriate completion code is set in the status register.

Ans4: After MAU has received the payload

Ans5: I will check with my team and get back to you.

Thanks,

0 Gabriele_Giannini over 9 years ago in reply to Ganapathi Dhandapani95

Intellectual 925 points

Ganapathi Dhandapani said:

Ans1: Yes it is possible, You need to set equal priority to each LSU.

Where is the LSU priority selected? From LSU_Reg4? Isn't that priority field for the priority of transaction?

And so, if i Write with a single Core multiple consecutively transactions in the shadow registers of all the LSU, from LSU0 to LSU7 (LSU0 Transaction1, LSU1 Transaction2, LSU2 Transaction3 and so on...), will i have output in SRIO bus a perfect FIFO order, right?

0 Ganapathi Dhandapani95 over 9 years ago in reply to Gabriele_Giannini

TI__Mastermind 28085 points

Hi,

Yes, you need to set LSU priority in LSU_Reg4.

Yes, Transfer from TX FIFO to external device based on FIFO order.

Thanks,

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Questions about SRIO (C6678)