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DDR3 connecting to c6671

Hello,

I checked the circuit of c6678 evaluation board. There are five DDR3 memories on eva board, but I will use three DDR3.

I don't have any experience about DDR3, so I need some advice relating below.

Q1> Please check my design plan

The DDR3 I will use is 2Gbit with 16bit data lines. I will use three DDR3 - two is for data and one is for ECC.

Data line: I will connect only 32bit(DDRD00~DDRD31] to DDR3 and let  DDRD32~DDRD63 floating.

Address line: I will connect DDRA00~DDRA13 to DDR3 and let DDRA14~DDRA15 floating.

ECC: I will connect DDRCB00~DDRCB03 to DDR3 and let DDRCB04~DDRCB07 floating

Data strobe: I will connect DQS0/1 to first data DDR3, DQS2/3 to second DDR3 and DQS8 to ECC

Q2> On the eva b'd circuit, there is comment about fly-by routing order. The order is '0, 1, 2, 3, ECC, 4, 5, 6, 7'

I don't understand what the number(0 ~ 7) mean. 

There are three DDR3 on my application. Let me know the order for my application.

  • Hello Kim,

    On the eva b'd circuit, there is comment about fly-by routing order. The order is '0, 1, 2, 3, ECC, 4, 5, 6, 7'

    The relative position of the memory components on the fly-by chain is determined by the position of the data lanes on the SOC foot print. If you look at the footprint you will see that the ECC byte lane is in the center, next to the address and command lanes. This position was based on the location of the ECC in the pinout of a UDIMM. Ordering the byte lanes in this fashion allows the data lanes to be routed directly to the DDR3 memory devices or to the UDIMM socket without the lanes crossing each other.

    Based on above statement, you can follow the order 0, 1, 2, 3, ECC for your requirement.

    Regards,

    Senthil

  • Thank you for your answer.

    Can I get answers for my first questions about connecting?

  • Hello Kim,

    Your DDR3 interface connections plan seems to be good for three memory chips.

    Regards,

    Senthil