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MCBSP_DigLpbkExampleProject on C6657EVM

Hi all,

I refer McBSP example project to verify hardware signal on C6657EVM.

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PATH: BIOS-MCSDK_02_01_02_05\pdk_C6657_1_1_2_5\packages\ti\drv\exampleProjects\MCBSP_DigLpbkExampleProject

========================================================================

But I observed the FS signal(yellow one) seemed abnormal.  Could someone help this query? Thanks in advance.

B.R.

OC

  • Hi OC,

    I would recommend you to use latest MCSDK released for Keystone I devices. Please find the download and user guide link below signature.

    In the meantime, I will work with our expert to look into above issue.

    Thank you for your patience.

  • Hi OC,

    Can you be more specific? The frame sync signal appears to be valid to me but it can be programmed in many ways. What were you expecting to see?

    Regards, Bill

  • Dear Bill,

    the picture which is provided by OC, the frame sync signal is abnormal.

    the low level voltage is almost 1~1.2 V.
    the high level voltage is almost 1.8 V.

    is the low level voltage is needed to be 0 V, right?

    how do you think about this?

    Jeff

  • Hi all,

    I also checked C6657EVM schematic again. The McBSP pins connected to FPGA and output the signal through FPGA's I/O pins. So, I concerned FPGA's I/O pins to affect this output result. Could someone help to confirm that?

    Thanks in advance.

    B.R.

    OC

     

  • Hi OC,

    By default, the C6657EVM  McBSP framesync and clock are driven by the FPGA based on the signals inputs from the AMC connector. This is described in detail in the section 2.14 of the technical reference manual for the EVM. This feature can be disabled if you are driving the MCBSP interface from the expansion connector.

    Are you currently driving the interface from the expansion connector or are you measuring the output of the FPGA? Note that when the FPGA is driving the McBSP signals, the frame syncs and clocks should be configured to be inputs to the SOC.

    Regards, Bill

  • Hi Bill,

    when use the sample code, we got some result as following.

     

    Test 1: the settings is default settings

    /**< clock setup for the TX section                     */

    Mcbsp_ClkSetup mcbspClkConfigTx =

    {

        Mcbsp_FsClkMode_INTERNAL,

        96000,                   /* 96KHz                   */

        Mcbsp_TxRxClkMode_INTERNAL,

        Mcbsp_FsPol_ACTIVE_HIGH,

        Mcbsp_ClkPol_RISING_EDGE

    };

     

    /**< clock setup for the RX section                     */

    Mcbsp_ClkSetup mcbspClkConfigRx =

    {

        Mcbsp_FsClkMode_EXTERNAL,

        96000,                   /* 96KHz                   */

        Mcbsp_TxRxClkMode_EXTERNAL,

        Mcbsp_FsPol_ACTIVE_HIGH,

        Mcbsp_ClkPol_FALLING_EDGE

    };


    Tx signal (yellow: frame sync, blue: BCLK)

    it is normal now. (the expected result)

    Rx signal (yellow: frame sync, blue: BCLK)

    the frame sync: no output pulse

    the bclk is abnormal (the voltage is almost 0~0.2V)

    Test 2: (base on Test 1, change RX settings, using internal frame sync and bclk)

    /**< clock setup for the TX section                     */

    Mcbsp_ClkSetup mcbspClkConfigTx =

    {

        Mcbsp_FsClkMode_INTERNAL,

        96000,                   /* 96KHz                   */

        Mcbsp_TxRxClkMode_INTERNAL,

        Mcbsp_FsPol_ACTIVE_HIGH,

        Mcbsp_ClkPol_RISING_EDGE

    };

     

    /**< clock setup for the RX section                     */

    Mcbsp_ClkSetup mcbspClkConfigRx =

    {

        Mcbsp_FsClkMode_INTERNAL,

        96000,                   /* 96KHz                   */

        Mcbsp_TxRxClkMode_INTERNAL,

        Mcbsp_FsPol_ACTIVE_HIGH,

        Mcbsp_ClkPol_FALLING_EDGE

    };

     

    Tx signal is the same as Test 1,

     

    Rx signal (yellow: frame sync, blue: BCLK)

    the frame sync is normal.

    the bclk is abnormal. (the voltage is almost 0 ~ 0.2V)

    Test 3: (base on Test 1, change RX settings, using Mcbsp_FsClkMode_DXR_XSR frame sync and internal bclk)

    /**< clock setup for the TX section                     */

    Mcbsp_ClkSetup mcbspClkConfigTx =

    {

        Mcbsp_FsClkMode_INTERNAL,

        96000,                   /* 96KHz                   */

        Mcbsp_TxRxClkMode_INTERNAL,

        Mcbsp_FsPol_ACTIVE_HIGH,

        Mcbsp_ClkPol_RISING_EDGE

    };

     

    /**< clock setup for the RX section                     */

    Mcbsp_ClkSetup mcbspClkConfigRx =

    {

        Mcbsp_FsClkMode_DXR_XSR,

        96000,                   /* 96KHz                   */

        Mcbsp_TxRxClkMode_INTERNAL,

        Mcbsp_FsPol_ACTIVE_HIGH,

        Mcbsp_ClkPol_FALLING_EDGE

    };

     

    Tx signal is the same as Test 1.

     

    Rx signal is the same as Test 1.

    the frame sync: no output any pulse

    the bclk is abnormal. (the voltage is almost 0 ~ 0.2V)

     

     

    above the three test, we have some questions, need you to help

    1. in Test 2, the Rx is master mode, it must generate the output signal, but the result is not expected. what's wrong?

    2. in Test 3, the Rx is set to Mcbsp_FsClkMode_DXR_XSR, does the Rx generate the output signal or not?

    3. in our use, the external audio codec (TLV320AIC3105EVM), the WCLK (FST/FSR) is the same pin. the BCLK (TxCLK/RxCLK) is also the same pin. In C6657, can we share WCLK pin for FST/FSR and BCLK pin for TxCLK/RxCLK?


    Jeff