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C6678 as EP does not enumerate on PCIe

Martin Leister
Prodigy 100 points

We are having issues getting our C6678 to enumerate on the PCIe bus.

The 6678 is configured as a PCIe Endpoint on our custom card, and it appears that at sometime during the enumeration process, the PCIe state machine (LTSSM) in the DSP is disabled (LTSSM_EN = 0).
We suspect that this occurs when the DSP receives a PCIe Hot Reset sometime during enumeration.
We are booting up in PCIe mode, so there is no code running that would allow the DSP to re-enable the LTSSM.

We took a look at the TI Forum, and identified a couple of posts that appear to be related to ours:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/348306.aspx?pi303753=1
Eventually gives a hint that the PCIe reset ( PERST#) needs to reset the DSP, and that monitoring LTSSM and resetting LTSSM_EN is needed if PERST# isn't there(?)

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/221855/783786.aspx#783786
Here the discussion is about a system with 2 FPGAs and 2 DSPs and a switch card, and the DSPs don't enumerate but the FPGA's do. This is similar to what we are seeing in our system.
The user eventually states that he sent a hot reset to the DSP, and the LTSSM state went to 0, which matches our suspicion.

Also, in section 2.11.2.1, step 6 of SPRUG56C states "Upon reset, the LTSSM_EN is de-asserted automatically
by hardware." I am not sure which reset they are talking about.

Is it true that the C6678 DSP LTSSM is disabled after receiving a Hot Reset?
If so, how should this issue be dealt with if booting over PCIe, and there is no DSP SW running?

  • 0
    TI__Mastermind 28085 points

    Hi Martin,

    Please provide more information about your test setup.

    1. Have you connect the C6678 device to Host PC and configure DSP as EP& Host PC as RC? please provide your setup datail

    2. Have you using TI provide example project for your testing?

    Yes, LTSSM is disabled after receiving a Hot Reset.

    Please take a look at Usage Note 1 on Silicon Errata document

    http://www.ti.com/lit/er/sprz334g/sprz334g.pdf

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 100 points

    Hi Ganapathi -

    1.
    Yes the PC is acting as the Root Port, and the 6678 DSP is configured as an Endpoint.

    2.
    We are running the 6678 DSP in PCIe Boot Mode, so there is no SW running.

    The PCIESSEN on the DSP is tied high, so Usage Note 1 in the Silicon Errata document is not relevant

    What is relevant is that the LTSSM is disabled after receiving a Hot Reset. Shouldn't this be in the Silicon Errata document? The PCI Express Base Specification states that the LTSSM should transition to the Detect state 2ms after receiving a Hot Reset. So it appears that the TI 6678 DSP violates the PCI Express spec.

    In our experience with various Root Ports, we have seen that a Hot Reset is transmitted as part of the enumeration process.

    How is the TI 6678 DSP in PCIe Boot Mode supposed to be able to enumerate as a PCIe Endpoint if it disables the LTSSM during enumeration?

    Regards,

    - Marty

  • 0 in reply to Martin Leister
    TI__Mastermind 28085 points

    Hi Martin,

    C6678 enumeration with PC host means the following power up sequence is required, Please check the power sequence on your setup.

    1. PCIe slot on PC host provides power and reference clock to PCIe module on C6678.

    2. PCIe boot code on C6678 initializes C66x PCIe module and ready for link up.

    3. PCIe root complex in PC host is powered up and link up is established between PCIe root complex (RC) in host and PCIe end point (EP) in C6678.

    4. PC host enumeration (BIOS) starts to scan the PCIe bus.

    5. PCIe end point in C6678 is enumerated and registered in PC host OS.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 100 points

    Hi Ganapathi,

    I have modified the power-up sequence below to show what we are seeing:

    1. PCIe slot on PC host provides power and reference clock to PCIe module on C6678.

    2. PCIe [internal ROM] boot code on C6678 initializes C66x PCIe module and ready for link up.

    3. PCIe root complex in PC host is powered up and link up is established between PCIe root complex (RC) in host and PCIe end point (EP) in C6678.

    3a. PCIe root complex in the PC host sends a Hot Reset

    3b. C6678 C66x PCIe module disables the LTSSM.

    4. PC host enumeration (BIOS) starts to scan the PCIe bus.

    5. PCIe end point in C6678 is enumerated and registered in PC host OS.

    5. PCIe end point in C6678 does not respond to PC host enumeration since the LTSSM is disabled.

    Please let us know how to resolve this issue.

    Regards,

    - Marty

  • 0 in reply to Martin Leister
    TI__Guru* 84110 points

    One clarification made in step 2, that the boot code is the internal ROM, not an IBL. The defaults from the ROM code are what are being applied to the PCIe peripheral.

    Regards,
    RandyP

  • 0 in reply to RandyP
    TI__Guru* 95265 points

    Marty,

    Do you use TI 6678EVM card or your customized board in a PC for PCIE enumeration? It is a known issue for 6678 reliably detected, the IBL has to be used, the ROM bootloader in PCIE EP boot mode may not work. Do you have some non-volatile memory (EEPROM/NAND/NOR) on your card?

    Regards, Eric

     

  • 0 in reply to lding
    Prodigy 100 points

    Hi Eric -

    Our board is custom.

    The 6678 DSP SPI port is tied to an FPGA that is configured prior to the de-assertion of DSP reset. So IBL code can be downloaded through the DSP SPI port if that is a possibility.

    Regards,

    - Marty

  • 0 in reply to Martin Leister
    TI__Guru* 95265 points

    Marty,

    Yes, please flash the IBL code to your FPGA and boot from SPI. That is the solution.

    Regards, Eric

  • 0 in reply to lding
    Prodigy 100 points

    Eric -

    Please let me know the location of the IBL code. Are there instructions on how to configure the DSP to run the IBL code from the SPI port?

    Does the IBL code re-enable the LTSSM after it is disabled but a Hot Reset?

    Regards,

    - Marty

  • 0 in reply to Martin Leister
    TI__Guru* 95265 points

    Marty,

    - IBL is under: ti\mcsdk_2_01_02_06\tools\boot_loader\ibl, there is instructions to how to rebuild IBL in case you needed.

    - The pre-built IBL image is under \mcsdk_2_01_02_06\tools\program_evm\binaries\evm6678l\eeprom51.bin, we used eepromwriter_evm6678l.out tool to write it into EEPROM on our 6678 EVM. The instruction is mcsdk_2_01_02_06\tools\program_evm\program_evm_userguide.pdf

    The IBL code doesn't re-enable the LTSSM, I believe the boot from IBL (it is via I2C) in our EVM is slow due to I2C speed. From the timing, the link training of DSP's PCIE is enabled AFTER the PC's hot reset, so there is no issue for enumeration.

    In rare cases, the PCIE link does failed due to hot reset even using IBL, you can verify this by looking at LTSSM_EN bit is 0. 

    What you can do is to re-enable LTSSM_EN once: The code is mcsdk_2_01_02_06\tools\boot_loader\ibl\src\device\c66x\c66xinit.C, search for iblPCIeWorkaround()

        DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_CMD_STATUS), 0x0000007);    /* enable LTSSM, IN, OB */
        while((DEVICE_REG32_R(PCIE_BASE_ADDR + PCIE_DEBUG0) & 0x11)!=0x11);    /* Wait for training to complete */
     

     After here, wait for some time, maybe hundreds of ms. Check the LTSSM in DEBUG0 register again for bits 0-4, if it is not 0x11, then re-enable the link training by writing 1 to LTSSM_EN, this should work. Modifying the IBL code means you need to rebuild it.

    Regards, Eric